Motorola MPC860 PowerQUICC User Manual page 758

Part V. The Communications Processor Module
MPC860
System
Bus SCC
TENA (RTS)
TCLK (CLKx)
RENA (CD)
RCLK (CLKx)
CLSN (CTS)
RSTRT
REJECT
Parallel I/O
PB[16:23]
SDACK1/SDACK2
Optional Frame
Buffers
NOTE: The receive data is sent directly from the EEST serial interface to the CAM using RXD and RCLK. RSTRT is
asserted at the beginning of the destination address. REJECT should be asserted during the frame to cause the
frame to be rejected. The system bus is used for CAM initialization and maintenance.
Start Frame
RxD
Preamble
7 Bytes
RSTRT
REJECT
Asserted on Second Destination Address Bit
Figure 28-4. MPC860 Ethernet Serial CAM Interface
28.7.2 Parallel CAM Interface
The MPC860 outputs SDACK1 and SDACK2 whenever it writes Ethernet frame data to
system memory. They are asserted during all bus cycles on which Ethernet frame data is
written to memory and are not used for other protocols. The CAM control logic uses these
signals simultaneously to enable the CAM writes with system memory writes. The
advantage of the CAM capturing frame data as it is written to system memory is that the
data is already in parallel form when it leaves the MPC860. Figure 28-5 shows a parallel
interface conÞguration.
28-10
TXD
RXD
Shift Register
Tag Byte
and
CAM Control
Destination Source
Delimiter Address Address
1 Byte 6 Bytes 6 Bytes
for a Duration of 1-Bit Time
MPC860 PowerQUICC UserÕs Manual
EEST
MC68160
Tx
TENA
TCLK
Rx
RENA
RCLK
Passive
CLSN
Loop
CAM
Type/
Data
Length
2 Bytes 46Ð1500 Bytes
Frame Rejected if Asserted During Frame Reception.
Further Transmissions on System Bus Cease,
and Buffer Descriptors are Reused.
To Media
Frame Check
Sequence
4 Bytes
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