Motorola MPC860 PowerQUICC User Manual page 364

Part IV. Hardware Interface
CLKOUT
BR
BG
BB
A[0Ð31]
R/W
TSIZ[0Ð1], AT[0Ð3]
BURST
TS
Data
TA
Figure 14-9. Basic Timing: Single-Beat Write Cycle, One Wait State
The general case of single-beat transfers assumes that external memory has a 32-bit port
size. The MPC860 provides an effective mechanism for interfacing with 16- and 8-bit port
size memories by allowing transfers to these devices when they are controlled by the
internal memory controller.
14-12
Receive BG and BB negated
Assert BB, drive address and assert TS
Wait State
MPC860 PowerQUICC UserÕs Manual
Data is Sampled
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