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Appendixes
Table A-5. Little-Endian Program/Data Path between the Register and
Fetch/
U-bus
Little-
Load
and
Endian
Store
Cache
Addr
Type
Addr
Word
0
Half-word
0
Half-word
2
Byte
0
Byte
1
Byte
2
Byte
3
A.5 PPC-LE Mode
For PPC-LE mode, the caches, the U-bus, and the external bus use big-endian byte ordering
with munged addresses. The byte-ordering mechanisms for PPC-LE mode are shown in
Figure A-3.
A-6
8-Bit Memory
Data in the
Register
External
Bus
M
Addr
S
B
0
0
11 12 13 14 11 12 13 14 14
1
2
3
2
0
1
0
2
3
3
0
2
1
1
2
0
3
MPC860 PowerQUICC UserÕs Manual
U-bus and
Cache Format
L
S
0
1
2
3
B
21 22
21 22 22
31 32 31 32
ÔaÕ
ÔaÕ ÔaÕ
ÔbÕ
ÔbÕ
ÔcÕ
ÔcÕ
ÔdÕ ÔdÕ
External Bus
Little-Endian
Format
Program/Data
0
1
2
3
3
2
13
12
11
21
32
31
ÔbÕ
ÔcÕ
ÔdÕ
MOTOROLA
1
0
14
13
12
11
22
21
32
31
ÔaÕ
ÔbÕ
ÔcÕ
ÔdÕ
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