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If the memory region is marked caching-inhibited or the cache is locked, and the access
misses, then the lwarx instruction appears on the bus as a single-beat load with the
reservation.
lwarx and stwcx. accesses to write-through memory regions do not generate DSI
exceptions. The MPC860Õs data cache treats all stwcx. operations as write-through
independent of the memory/cache access attributes. When the write-through operation
completes successfully on the external bus, then the data cache entry is updated (assuming
it hits), and CR0[EQ] is modiÞed to reßect the success of the operation. If the reservation
is not intact, the stwcx. cancels the external bus transaction, and the cache block is not
altered.
8.7 Cache Initialization after Reset
At power-on and hard reset, both caches are disabled. Although disabled, the cache state is
preserved to enable the user to investigate the exact state of the cache prior to the event that
caused the reset. To ensure proper operation after reset, initialize the instruction cache by
performing the following:
1. Write the unlock all command (IC_CST[CMD] = 0b101) to the IC_CST register
2. Write the invalidate all command (IC_CST[CMD] = 0b110) to the IC_CST register
3. Write the cache enable command (IC_CST[CMD] = 0b001) to the IC_CST register
Similarly, to ensure proper operation after reset, initialize the data cache by performing the
following:
1. Write the unlock all command (DC_CST[CMD] = 0b1010) to the DC_CST register
2. Write the invalidate all command (DC_CST[CMD] = 0b1100) to the DC_CST
register
3. Write the cache enable command (DC_CST[CMD] = 0b0010) to the DC_CST
register
After the caches are initialized, all the cache blocks are invalidated, and the LRU bits point
to way 0 of each set.
8.8 Debug Support
The MPC860 can be debugged either in debug mode or by a software monitor debugger. In
both cases the core of the MPC860 asserts the internal freeze signal. See Chapter 37,
ÒSystem Development and Debugging,Ó for a detailed description of the MPC860 debug
support.
8.8.1 Instruction and Data Cache Operation in Debug Mode
The development system interface of the MPC860 uses the development port, which is a
dedicated serial port. The development port is a relatively inexpensive interface that allows
MOTOROLA
Chapter 8. Instruction and Data Caches
Part II. PowerPC Microprocessor Module
8-29
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