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16.7.1 Hierarchical Bus Interface Example
Assume that the CPU initiates a local-bus read cycle that addresses main memory
connected to the system bus. The hierarchical bus interface accepts local bus requests and
generates a read cycle on the system bus. The programmer cannot predict when valid data
can be latched by the CPU because a DMA device may be occupying the system bus.
¥ The wait solution (UPM)ÑThe external module asserts UPWAIT to the memory
controller to indicate that data is not ready. The memory controller synchronized this
signal because the wait signal is asynchronous. As a result of the wait signal being
asserted, the UPM enters a freeze mode at the falling edge of CLKOUT upon
encountering the WAEN bit being set in the UPM word. The UPM stays in that state
until UPWAIT is asserted. After UPWAIT is negated, the UPM continues executing
from the next entry to the end of the pattern (LAST bit is set).
¥ The external TA solution (GPCM)ÑThe bus interface module asserts TA to the
memory controller when it can sample data.
16.7.2 Slow Devices Example
Assume the CPU initiates a read cycle from a device whose access time exceeds the
maximum allowed by the user programming model.
¥ The wait solution (UPM)ÑThe CPU generates a read access from the slow device.
The device in turn asserts the wait signal as long as the data is not ready. The CPU
samples data only after the wait signal is negated.
¥ The external TA solution (GPCM)ÑThe CPU generates a read access from the slow
device, which must generate the synchronous TA when it is ready.
16.8 External Master Support
The memory controller supports internal and external bus masters. Accesses from the core
or the CPM are considered internal; accesses from an external bus master are external.
External bus master support is available only if enabled in the SIU module conÞguration
register (SIUMCR), described in Section 11.4.2. There are two types of external bus
masters:
¥ Synchronous bus masters synchronize with CLKOUT and may or may not use the
MPC860 memory controller to access a slave.
¥ Asynchronous bus masters use an address strobe signal (AS) that handshakes with
the MPC860 memory controller to access a slave device or bypass the memory
controller to perform the slave access.
16.8.1 Synchronous External Masters
Synchronous masters initiate a transfer by asserting TS. A[0Ð31], RD/WR, BURST, and
TSIZ must be stable before the rising edge of CLKOUT after TS is asserted and until the
last TA is negated. Because the external master operates synchronously with the MPC860,
MOTOROLA
Chapter 16. Memory Controller
Part IV. Hardware Interface
16-51
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