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Part IV. Hardware Interface
UPMA
UPMB
The uppermost byte select (BS0) indicates that D[0Ð7] contains valid data during a cycle.
Likewise, BS1 indicates that D[8Ð15] contains valid data, BS2 indicates that D[16Ð23]
contains valid data, and BS3 indicates that D[24Ð31] contains valid data during a cycle.
Table 16-14 shows how BS signals affect 32-, 16-, and 8-bit accesses. Note that for a
periodic timer request and a memory command request, the BS signals are determined only
by the port size of the bank.
Transfer
TSIZ
Size
A30
Byte
0
1
0
1
0
1
0
1
Half-Word
1
0
1
0
Word
0
0
16.6.4.4 General-Purpose Signals (GxTx, GOx)
The general-purpose signals (GPL[1Ð5]) have two bits in the RAM word that deÞne the
logical value of the signal to be changed at the falling edge of GCLK1_50 or GCLK2_50.
GPL0 has two 2-bit Þelds that perform this function plus an additional function explained
below. GPL5 and GPL0 offer the following enhancements beyond the other GPLx signals:
¥ GPL5 can be controlled during phase 4 of the Þrst clock cycle according to the value
of G5LS, as shown in Figure 16-42. This allows it to assert earlier (simultaneous
with TS, for an internal master), which can speed up the memory interface,
particularly when GPL5 is used as a control signal for external address multiplexers.
16-40
Bank Selected
MS[0Ð1] in BRx
MUX
Figure 16-41. BS Signal Selection
Table 16-14. Enabling Byte-Selects
Address
32-Bit Port Size
A31
BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3
0
0
X
0
1
X
1
0
1
1
0
0
X
X
1
0
0
0
X
X
MPC860 PowerQUICC UserÕs Manual
A[30Ð31]
TSIZ[0Ð1]
PS[0Ð1] in BRx
Byte-Select
Logic
16-Bit Port Size
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BS0
BS1
BS2
BS3
8-Bit Port Size
X
X
X
X
X
X
X
MOTOROLA
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