Motorola MPC860 PowerQUICC User Manual page 456

Part IV. Hardware Interface
Note also the following:
¥ Address incrementing is not provided in this mode. Addresses driven by the
MPC8560 remain the same throughout the cycle.
¥ The external slave must provide TA for all beats of the burst.
16.6 User-Programmable Machines (UPMs)
The two user-programmable machines (UPMs) are ßexible interfaces that connect to a wide
range of memory devices. At the heart of each UPM is an internal-memory RAM array that
speciÞes the logical value driven on the external memory controller pins for a given clock
cycle. Each word in the RAM array provides bits that allow a memory access to be
controlled with a resolution of one quarter of the external bus clock period on the
byte-select and chip-select lines. Figure 16-31 shows the basic operation of each UPM. The
following events initiate a UPM cycle:
¥ Any internal or external master requests an external memory access to an address
space mapped to a chip-select serviced by the UPM
¥ A UPM periodic timer expires and requests a transaction, such as a DRAM refresh
¥ A transfer error or reset generates an exception request
¥ The MCR receives a
Internal/External
Memory Access Request
UPM Periodic
Timer Request
MCR command (
RUN
issued in software)
Exception Request
Request
UPWAIT
Figure 16-31. User-Programmable Machine Block Diagram
The RAM array contains 64 32-bit RAM words. The signal timing generator loads the
RAM word from the RAM array to drive the general-purpose lines, byte-selects, and
chip-selects. If the UPM reads a RAM word with WAEN set, the external UPWAIT signal
is sampled and synchronized by the memory controller and the current request is frozen.
16-30
command from the CPU
RUN
Array
Index
Generator
Increment
Wait
(LAST = 0)
Hold
Logic
WAEN Bit
MPC860 PowerQUICC UserÕs Manual
Index
RAM Array
Index
Internal
Signals
Latch
Internal Controls
Signals
Timing
Generator
GPLx, BS_x, CSx
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