Motorola MPC860 PowerQUICC User Manual page 204

Part II. PowerPC Microprocessor Module
affect the instruction address translation logic; MSR[IR] controls instruction address
translation.
At hard reset, the instruction cache is disabled.
8.3.1.2.2 Instruction Cache Load & Lock Cache Block Command
The instruction cache load & lock cache block command (IC_CST[CMD] = 0b011) is used
to lock critical code segments in the instruction cache. Locked cache blocks are not
replaced during misses and are not affected by invalidate commands. Correct operation of
locked instruction cache blocks relies on software following the procedures described in
Section 8.5.5, ÒUpdating Code And Memory Region Attributes.Ó
To load & lock one or more cache blocks:
1. Read the IC_CST error type bits to clear them.
2. Write the address of the cache block to be locked to the IC_ADR register.
3. Write the load & lock cache block command (IC_CST[CMD] = 0b011) to the
IC_CST register.
4. Execute an isync instruction.
5. Repeat steps 2 through 4 to load & lock another cache block.
6. Read the IC_CST error type bits to determine if the sequence completed without
errors.
After the load & lock cache block command is written to the IC_CST register, the cache
checks if the block containing the byte addressed by IC_ADR[ADR] is in the cache (hit).
If it is in the cache, the block is locked. If the block is not in the cache, a normal miss
sequence is initiated (see Section 8.5.2, ÒInstruction Cache Miss,Ó for more information).
After the addressed block is placed into the cache, the block is locked.
The user must check the IC_CST error type bits to determine if the load & lock cache block
operation completed without error. The load & lock cache block command generates two
possible errors:
¥ Type 1Ña bus error occurred in one of the fetch cycles
¥ Type 2Ñthere is no available way to lock (It is the responsibility of the user to make
sure that there is at least one unlocked way in the appropriate set.)
The error type bits in the IC_CST register are sticky, thus allowing the user to perform a
series of load & lock cache block commands before checking the termination status. These
bits are set by the MPC860 and are cleared by software.
Note that the MPC860 considers all zero-wait-state devices on the internal bus as
caching-inhibited. For this reason, software should not perform load & lock cache block
operations from these devices on the internal bus.
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