Motorola MPC860 PowerQUICC User Manual page 475

next falling GCLK2_50 edge as programmed in the RAM word until UPWAIT is negated.
This allows wait states to be inserted as required by an external device through an external
signal.
Figure 16-45 shows how the WAEN bit in the word read by the UPM and the UPWAIT
signal are used to hold the UPM in a particular state until UPWAIT is negated. As the
example in Figure 16-45 shows, the CSx and GPL1 states (C12 and F) and the WAEN value
(CC) are frozen until UPWAIT is recognized as deasserted.
CLKOUT
GCLK1_50
GCLK2_50
CSx C1 C2 C3
GPL1 A
TA
WAEN AA
UPWAIT
RAM
Word N
Figure 16-45. Wait Mechanism Timing for Internal and External Synchronous
16.6.4.11.2 External Asynchronous Masters
For an external asynchronous master, AS is the external signal that activates the wait
mechanism. The UPM enters a wait state if AS was sampled asserted on the previous falling
edge of GLCK2_50 and WAEN = 1 in the current RAM word. In this wait state, external
signals are frozen after the falling edge of GCLK2_50, as programmed in the RAM word
in which WAEN is set. This is demonstrated in the example in Figure 16-46 in which the
CSx and GPL1 states (C12 and F) and the WAEN value (CC) are frozen until AS is
recognized as deasserted. The TA signal driven by the UPM also remains in its programmed
state until AS is negated. This allows TA to be used as an asynchronous handshake signal
by programming UTA = 0 in the same RAM word in which WAEN = 1. If this is done, TA
can be used to signal that AS should deassert (similar to DTACK in the 68000 bus).
The wait state is exited when AS is negated, at which point all external signals controlled
by the UPM are driven high asynchronously from the AS deassertion. External signals are
MOTOROLA
C4 C5 C6 C7 C8 C9
B C D
BB CC
RAM
Word N + 1 Word N + 2
Masters
Chapter 16. Memory Controller
C10 C11 C12
E F
RAM
WAIT
Part IV. Hardware Interface
C13
G
DD
RAM
WAIT
Word N
16-49
C14