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Table 7-16. Register Settings after a Data TLB Error Exception (Continued)
Register
DSISR
0
0
1
Set if the translation of an attempted access is not found in the translation tables. Otherwise, cleared
2Ð3
0
4
Set if the memory access is not permitted by the protection mechanism; otherwise cleared
5
0
6
1 for a store operation; 0 for a load operation.
7Ð31 0
DAR
Set to the EA of the data access that caused the exception.
Some instruction TLB registers are set to the values described in Chapter 9, ÒMemory
Management Unit (MMU).Ó Execution resumes at offset 0x01400 from the base address
indicated by MSR[IP].
7.1.3.6 Debug Exceptions (0x01C00Ð0x01F00)
A debug exception occurs in response to one of the following conditions:
¥ When there is an internal breakpoint match (for more details, see Section 37.2,
ÒWatchpoints and Breakpoints SupportÓ).
¥ When a peripheral breakpoint request is presented to the exception mechanism.
¥ When the development port request is presented to the exception mechanism.
The following registers are set:
Table 7-17. Register Settings after a Debug Exception
Register
SRR0
For I-breakpoints, set to the EA of the instruction that caused the exception. For L-breakpoint, set to the EA
of the instruction after the one that caused the exception. For development port maskable request or a
peripheral breakpoint, set to the EA of the instruction that the processor would have executed next if no
exception conditions were present. If the development port request is asserted at reset, the value of SRR0
is undeÞned.
SRR1
1Ð4
0
10Ð15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
If the development port request is asserted at reset, the value of SRR1 is undeÞned.
MSR
IP
No change
ME
No change
LE
Copied from the ILE setting of the interrupted process
Others 0
BAR
For L-bus breakpoint conditions. Set to the EA of the data access as computed by the instruction that
caused the exception.
DSISR
For L-bus breakpoint conditions. Do not change.
DAR
For L-bus breakpoint conditions. Do not change.
MOTOROLA
Part II. PowerPC Microprocessor Module
Setting
Setting
Chapter 7. Exceptions
7-15
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