Motorola MPC860 PowerQUICC User Manual page 288

Part III. Configuration
11.5.2 Priority of Interrupt Sources
There are eight external IRQ pins (IRQ0 is essentially nonmaskable, although in a limited
sense it can be masked as shown in Table 11-8) and eight interrupt levels. Asserting IRQ0
causes an NMI. The other 15 interrupt sources assert a single interrupt request to the core
(the external interrupt). Table 11-7 shows interrupt priorities.
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
11-14
Table 11-7. Priority of SIU Interrupt Sources
Priority Level Interrupt Source
Highest
Lowest
MPC860 PowerQUICC UserÕs Manual
IRQ0
Internal Level 0
IRQ1
Internal Level 1
IRQ2
Internal Level 2
IRQ3
Internal Level 3
IRQ4
Internal Level 4
IRQ5
Internal Level 5
IRQ6
Internal Level 6
IRQ7
Internal Level 7
Reserved
Interrupt Code
(SIVEC[INTC])
0000_0000
0000_0100
0000_1000
0000_1100
0001_0000
0001_0100
0001_1000
0001_1100
0010_0000
0010_0100
0010_1000
0010_1100
0011_0000
0011_0100
0011_1000
0011_1100
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