Motorola MPC860 PowerQUICC User Manual page 478

Part IV. Hardware Interface
meeting setup and hold times for all inputs associated with the rising edge of CLKOUT is
critical. To support synchronous mode using the memory controller, SIUMCR[SEME]
must be set. When TS is asserted, the memory controller compares the address with each
of its valid banks. If a match is found, control signals to the slave are generated and TA is
supplied to the external master. If SEME = 0, the memory controller is bypassed and the
external synchronous master must provide control signals to the slave. See Figure 16-47.
16.8.2 Asynchronous External Masters
Asynchronous masters initiate transfers by driving the address bus and asserting AS.
A[0Ð31], RD/WR, and TSIZ must have a proper setup time before AS is asserted. To
support asynchronous mode, SIUMCR[AEME] must be set. The memory controller
synchronizes AS assertion to its internal clock and generates control signals to the slave
device. When AS is synchronized, the memory controller compares the address with each
of its deÞned valid banks; if a match is found, control signals to the slave are generated and
TA is supplied to the external master. All control signals to the memory device and TA are
negated with the negation of AS. If AEME = 0, the memory controller is bypassed and the
external asynchronous master must provide control signals to the slave. In this mode, the
MPC860Õs AS signal cannot be used as an input. See Figure 16-48.
16.8.3 Special Case: Address Type Signals for External Masters
The AT signals are not sampled on the external bus for external master accesses. When
external masters access slaves on the bus, the internal AT[0Ð2] signals reaching the memory
controller are forced to Ô100Õ. The user should ensure this access matches the BRx[AT]. It
is masked by ORx[ATM].
16.8.4 UPM Features Supporting External Masters
16.8.4.1 Address Incrementing for External Synchronous Bursting
Masters
BADDR[28Ð30] should be used to generate addresses to memory devices for burst
accesses. They duplicate the value of A[28Ð30] when an internal master initiates an external
bus transaction. When an external master initiates an external bus transaction, they reßect
the value of A[28Ð30] on the Þrst clock cycle of the memory access; these signals are
latched by the memory controller and on subsequent clock cycles, BADDR[28Ð30]
increments as programmed in the UPM.
16.8.4.2 Handshake Mechanism for Asynchronous Bursting Masters
A wait mechanism in the UPM supports handshaking for external asynchronous masters.
This is provided with an AS input signal and the WAEN bit in the UPM RAM words. See
Section 16.6.4.11, ÒThe Wait Mechanism (WAEN).Ó
16-52 MPC860 PowerQUICC UserÕs Manual MOTOROLA