Motorola MPC860 PowerQUICC User Manual page 705

TCLK
TXD
(Output)
CTS
(Input)
Figure 24-14. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance
24.14.4 Delayed RTS Mode
Figure 24-15 shows local HDLC bus controllers using a standard transmission line and a
local bus. The controllers do not communicate with each other but with a station on the
transmission line; yet the HDLC bus protocol controls access to the transmission line.
Rx
Line Driver
Tx
(1-Bit Delay)
EN
NOTES:
1. The TXD pins of slave devices should be conÞgured to open-drain in the port C parallel I/O port.
2. The RTS pins of each HDLC bus controller are conÞgured to delayed RTS mode.
Figure 24-15. HDLC Bus Transmission Line Configuration
Normally, RTS goes active at the beginning of the opening ßagÕs Þrst bit. Setting
PSMR[BRM] delays RTS by one bit, which is useful when the HDLC bus connects
multiple local stations to a transmission line. If the transmission line driver has a one-bit
delay, the delayed RTS can be used to enable the output of the line driver. As a result, the
electrical effects of collisions are isolated locally. Figure 24-16 shows RTS timing.
MOTOROLA
Part V. The Communications Processor Module
CTS sampled at three quarter point.
Collision detected when
TXD=1, but CTS=0.
Local HDLC Bus
RXD TXD CTS
HDLC Bus
Controller
A
RTS
Chapter 24. SCC HDLC Mode
+ 5 V
R
RXD TXD CTS
HDLC Bus
Controller
B
RTS
24-21