Motorola MPC860 PowerQUICC User Manual page 384

Part IV. Hardware Interface
Table 14-5. Address Types Definition (Continued)
CPU/ User/
STS TS CPM Supervisor
(AT0) (AT1)
x 1 0 0
1
1 AT1
ÔShow cyclesÕ are accesses to the CPUÕs internal bus devices. These accesses are made
visible externally for emulation and debugging. A show cycle can have one address phase
and one data phase (or just an address phase for the instruction show cycles). The cycle can
be a write or a read access. The address of the show cycle is valid on the bus for one clock
and the data of the show cycle is valid on the bus for one clock. The data phase does not
require a transfer acknowledge to terminate the bus-show cycle. In a burst-show cycle only
the Þrst data beat is shown externally.
When AT3 = 0 for an access from the core, it indicates either program trace (for an
instruction cycle) or reservation (for a data cycle). These indications can also be monitored
on two separate signals (PTR and RSV), if desired.
¥ PTR is low when the following is true:
Ñ AT0 = 0 (CPU access)
Ñ AT2 = 0 (Instruction)
Ñ AT3 = 0 (Program Trace)
14-32
Reservation/
Instruction/
Program
Data (AT2)
Trace (AT3)
0 0
1
1 0
1
0 0
1
1 0
1
AT2 AT3
MPC860 PowerQUICC UserÕs Manual
Program
Reservation
Trace Address Space DeÞnitions
(RSV)
(PTR)
0 1 Core-initiated, show cycle
address instruction,
program trace,
supervisor mode
1 1 Core-initiated, show cycle
address instruction,
supervisor mode
1 0 Core-initiated, reservation
show cycle data, supervisor
mode
1 1 Core-initiated, show cycle
data, supervisor mode
0 1 Core-initiated, show cycle
address instruction,
program trace,
user mode
1 1 Core-initiated, show cycle
address instruction, user
mode
1 0 Core-initiated, reservation
show cycle data, user mode
1 1 Core-initiated, show cycle
data, user mode
1 1 DMA-initiated, normal,
AT[1Ð3] user-programmable
(see IDMA and DMA
function code registers)
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