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Part V. The Communications Processor Module
Bits
0
1
2
Field
GR4 SC4
Reset
R/W
Addr
Bits
16
17
18
Field
GR2 SC2
Reset
R/W
Addr
Table 21-6 describes the SICR Þelds.
Bits
Name
0, 8, 16,
GRx
Grant support of SCCx.
24
0 Transmitter does not support the grant mechanism. The grant is always asserted internally.
1 Transmitter supports the grant mechanism as determined by SIMODE[GMx].
1, 9, 17,
SCx
SCCx connection.
25
0 SCCx is not connected to the TSA. It is either connected directly to the NMSI pins or is not used.
The choice of general-purpose I/O port versus SCCx functionality is made in the parallel I/O
control register; see Chapter 34, ÒParallel I/O Ports.Ó
1 SCCx is connected to the multiplexed SI. NMSIx receive pins can be used for other purposes.
2Ð4,
RxCS
Receive/transmit clock source for SCCx. Ignored when SCCx is connected to the TSA (SCx = 1).
10Ð12,
000 BRG1.
18Ð20,
001 BRG2.
26Ð28
010 BRG3.
011 BRG4.
5Ð7,
TxCS
100 CLK1 for x = 1,2 and CLK5 for x = 3,4
13Ð15,
101 CLK2 for x = 1,2 and CLK6 for x = 3,4
21Ð23,
110 CLK3 for x = 1,2 and CLK7 for x = 3,4
29Ð31
111 CLK4 for x = 1,2 and CLK8 for x = 3,4
21.2.4.4 SI Command Register (SICMR)
The SI command register (SICMR) is used to swap the SI RAM routing. SICMR
commands are valid only when the SI RAM is partitioned for dynamic changes; that is,
when SIGMR[RDM] = 0b01 or 0b11. See Section 21.2.3.4, ÒSI RAM Dynamic Changes.Ó
21-24
3
4
5
6
R4CS
T4CS
19
20
21
22
R2CS
T2CS
Figure 21-20. SI Clock Route Register (SICR)
Table 21-6. SICR Field Descriptions
MPC860 PowerQUICC UserÕs Manual
7
8
9
10
GR3 SC3
R3CS
0
R/W
0xAEC
23
24
25
26
GR1 SC1
R1CS
0
R/W
0xAEE
Description
11
12
13
14
T3CS
27
28
29
30
T1CS
MOTOROLA
15
31
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