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¥ Maximum aggregate receive and transmit bandwidth of all SCCs of approximately
22 Mbps at 25-MHz system frequency (depending on protocol), scaling up linearly
with frequency. See Appendix B, ÒSerial Communications Performance.Ó
¥ Maximum serial clocking rates of 12.5 MHz on a 25-MHz system
¥ DPLL circuitry for clock recovery with NRZ, NRZI, FM0, FM1, Manchester, and
Differential Manchester (also known as Differential Bi-phase-L)
¥ Clocks can be derived from a baud rate generator, an external pin, or DPLL
¥ Data rate for asynchronous communication can be as high as 3.125 Mbps at 25 MHz
¥ Supports automatic control of the RTS, CTS, and CD modem signals
¥ Multi-buffer data structure for receive and send (the number of buffer descriptors
(BDs) is limited only by the size of the internal dual-port RAMÑ8 bytes per BD)
¥ Deep FIFOs (The SCC1 transmit and receive FIFOs are 32 bytes each; SCC2ÐSCC4
FIFOs are 16 bytes each.)
¥ Transmit-on-demand feature decreases time to frame transmission (transmit
latency)
¥ Low FIFO latency option for send and receive in character-oriented and totally
transparent protocols
¥ Frame preamble options
¥ Full-duplex operation
¥ Fully transparent option for one half of an SCC (Rx/Tx) while another protocol
executes on the other half (Tx/Rx)
¥ Echo and local loopback modes for testing
22.1.1 General SCC Mode Register (GSMR)
Each SCC contains a general SCC mode register (GSMR) that deÞnes options common to
each SCC regardless of the protocol. GSMR_L contains the low-order 32 bits; GSMR_H,
shown in Figure 22-2, contains the high-order 32 bits. Some GSMR operations are
described in later sections.
MOTOROLA
Chapter 22. Serial Communications Controllers
Part V. The Communications Processor Module
22-3
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