Motorola MPC860 PowerQUICC User Manual page 700

Part V. The Communications Processor Module
21. Write 0x001A to SCCM to allow TXE, RXF, and TXB interrupts.
22. Write 0x2000_0000 to the CPM interrupt mask register (CIMR) to allow SCC2 to
generate a system interrupt. The CICR should also be initialized.
23. Write 0x0000_0000 to GSMR_H2 to enable normal CTS and CD behavior with
idles (not ßags) between frames.
24. Write 0x0000_0000 to GSMR_L2 to conÞgure CTS and CD to control transmission
and reception in HDLC mode. Normal Tx clock operation is used. Notice that the
transmitter (ENT) and receiver (ENR) have not been enabled. If inverted HDLC
operation is preferred, set RINV and TINV.
25. Write 0x0000 to PSMR2 to conÞgure one opening and one closing ßag, 16-bit
CCITT-CRC, and prevent multiple frames in the FIFO.
26. Write 0x00000030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This
additional write ensures that ENT and ENR are enabled last.
Note that after 5 bytes and CRC have been sent, the Tx buffer is closed; the Rx buffer is
closed after a frame is received. Frames larger than 256 bytes cause a busy (out-of-buffers)
condition because only one RxBD is prepared.
24.13.2 SCC HDLC Programming Example #2
The following sequence initializes an HDLC channel that uses the DPLL in a Manchester
encoding. Provide a clock which is 16´ the chosen bit rate of CLK3. Then connect CLK3
to the HDLC transmitter and receiver. (A baud rate generator could be used instead.)
ConÞgure SCC2 to use RTS2, CTS2, and CD2.
1. Follow steps 1Ð23 in example #1 above.
2. Write 0x004A_A400 to GSMR_L2 to make carrier sense always active, a 16-bit
preamble of Ô01Õ patterns, 16´ operation of the DPLL and Manchester encoding for
the receiver and transmitter, and HDLC mode. CTS and CD should be conÞgured to
control transmission and reception. Do not set GSMR[ENT, ENR].
3. Write 0x0000 to PSMR2 to use one opening and one closing ßag and 16-bit
CCITT-CRC and to reject multiple frames in the FIFO.
4. Write 0x004A_A430 to GSMR_L2 to enable the SCC2 transmitter and receiver.
This additional write to GSMR_L2 ensures that ENT and ENR are enabled last.
24.14 HDLC Bus Mode with Collision Detection
The HDLC controller includes an option for hardware collision detection and
retransmission on an open-drain connected HDLC bus, referred to as HDLC bus mode.
Most HDLC-based controllers provide only point-to-point communications; however, the
HDLC bus enhancement allows implementation of an HDLC-based LAN and other
point-to-multipoint conÞgurations. The HDLC bus is based on techniques used in the
CCITT ISDN I.430 and ANSI T1.605 standards for D-channel point-to-multipoint
operation over the S/T interface. However, the HDLC bus does not fully comply with I.430
24-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA