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Bit
0
1
Field
S
Bit
16
17
Field
S
Figure 36-5. Complex Number Representation
36.5 Input and Output Buffers
The input and output buffers are circular in implementation with their sizes programmed in
the FD parameter packets. The input and output buffer lengths are (M + 1) and (N + 1)
bytes, respectively, where (M + 1) and (N + 1) are both multiples of 4.
The input and output buffers must each be aligned on natural boundaries in the dual-port
RAM. A natural boundary is an address evenly divisible by 2
size of the buffer. For example, an input buffer with a size of 24 bytes must reside in
dual-port RAM at an address evenly divisible by 32 (2
POINTER
36.6 Buffer and CoefÞcient Base Pointers (CBASE,
XPTR, XYPTR)
The input buffer, output buffer and coefÞcient buffer pointers are 16-bit offsets from the
base of the dual-port RAM. These include CBASE and the buffer pointers in the structures
pointed to by XPTR and XYPTR. The structures pointed to by XPTR and XYPTR consist
of a halfword-aligned array of the 16-bit pointers as deÞned by the particular DSP library
function.
36.7 DSP Parameter RAM
Two areas of the dual-port RAM hold the DSP parameters and scratchpad. The Rx chain
(DSP1) parameter area begins at the dual-port RAM offset 0x1EC0; the Tx chain (DSP2)
parameter area begins at 0x1FC0.
The FDBASE parameter deÞnes the starting address for the FD chain in system memory.
FDBASE should be 16-byte aligned and should be initialized before issuing
Table 36-3 shows the DSPx parameter RAM memory map.
MOTOROLA
2
3
4
5
18
19
20
21
22
DATA
Figure 36-6. Circular Buffer
Chapter 36. Digital Signal Processing
Part V. The Communications Processor Module
6
7
8
9
10
Imaginary
23
24
25
26
Real
z
, where 2
5
). See Figure 36-6.
BUFFER BASE ADDRESS (NATURALLY ALIGNED)
CIRCULAR
SIZE = (M +1) OR (N +1)
BUFFER
11
12
13
14
15
27
28
29
30
31
z
is greater than the
_
INIT
DSP
36-5
.
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