Table of Contents
Advertisement
Part V. The Communications Processor Module
22.1.2 Protocol-SpeciÞc Mode Register (PSMR)
The protocol implemented by an SCC is selected by its GSMR_L[MODE]. Each SCC has
an additional protocol-speciÞc mode register (PSMR) that conÞgures them speciÞcally for
the chosen protocol. The PSMR Þelds are described in the speciÞc chapters that describe
each protocol. PSMRs are cleared at reset.
22.1.3 Data Synchronization Register (DSR)
Each SCC has a data synchronization register (DSR) that speciÞes the pattern used for
frame synchronization. The programmed value for DSR depends on the protocol:
¥ UARTÑDSR is used to conÞgure fractional stop bit transmission.
¥ BISYNC and transparentÑDSR should be programmed with the sync pattern.
¥ EthernetÑDSR should be programmed with 0xD555.
¥ HDLCÑAt reset, DSR defaults to 0x7E7E (two HDLC ßags), so it does not need to
be written.
Figure 22-4 shows the sync Þelds.
Bit
0
1
2
Field
Reset
0
1
1
R/W
Addr
Figure 22-4.
22.1.4 Transmit-on-Demand Register (TODR)
In normal operation, if no frame is being sent by an SCC, the CP periodically polls the R
bit of the next TxBD to see if a new frame/buffer is requested. Depending on the SCC
conÞguration, this polling occurs every 8Ð32 serial Tx clocks. The transmit-on-demand
option, selected in the transmit-on-demand register (TODR) shown in Figure 22-5,
shortens the latency of the Tx buffer/frame and is useful in LAN-type protocols where
maximum interframe gap times are limited by the protocol speciÞcation.
Bit
0
1
Field
TOD
Reset
R/W
Addr
Figure 22-5. Transmit-on-Demand Register (TODR)
22-10
3
4
5
6
SYN2
1
1
1
1
0xA0E (DSR1), 0xA2E (DSR2,)0xA4E (DSR3), 0xA6E (DSR4)
Data Synchronization Register (DSR)
2
3
4
5
6
0xA0C (TODR1), 0xA2C (TODR2), 0xA4C (TODR3), 0xA6C (TODR4)
MPC860 PowerQUICC UserÕs Manual
7
8
9
10
0
0
1
1
R/W
7
8
9
10
Ñ
0
R/W
11
12
13
14
SYN1
1
1
1
1
11
12
13
14
MOTOROLA
15
0
15
Advertisement
Table of Contents
