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Example #3:
MPC860MH (at 25 MHz) running 32 QMC channels and one additional 2 Mbps HDLC
channel. The following equation applies:
Since the result above is greater than one, this will not work with a 25 MHz MPC860MH.
However, letÕs see what happens if we increase the frequency of the MPC860MH. If a
33-MHz system clock is used, CPM utilization will drop below 1, allowing example #3 to
be supported. The following equation applies:
Example #4:
MPC860 (at 25 MHz) with a block of data transferred by IDMA at 512 Kbytes/s to a 32-bit
peripheral, one asynchronous HDLC at 1Mbps, one UART at 9,600 baud, and one
transparent channel at 2 Mbps.
In the case of IDMA, this process calculates the peak CPM
utilization, not the sustained rate. By nature, IDMA transfers
occur at random intervals and are not consistent bit rates when
compared to the serial channel operation.
Example #5:
MPC860 (at 40 MHz) with three Ethernet channels at 10 Mbps and one UART at 9,600
baud.
MOTOROLA
´
æ ö
2
æ
32 0.064
ö
-- -
+
-------------------------
=
è ø
è
ø
8
2.1
æ
ö
25
´
----- -
1.22
=
è
ø
33
0.512
1
0.0096
5
3
NOTE:
3*10
0.0096
22
2.4
Appendix B. Serial Communications Performance
1.22
(will not work)
0.92
(<1)
2
0.69
2.4
8
25
0.85
1.37
X
40
Appendixes
B-7
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