Motorola MPC860 PowerQUICC User Manual page 122

Part II. PowerPC Microprocessor Module
systems, including battery-powered personal computers; embedded controllers; high-end
scientiÞc and graphics workstations; and multiprocessing, microprocessor-based
mainframes.
To provide a single architecture for such a broad assortment of processor environments, the
PowerPC architecture is both ßexible and scalable.
The ßexibility of the PowerPC architecture offers many price/performance options.
Designers can choose whether to implement architecturally-deÞned features in hardware or
in software. For example, a processor designed for a high-end workstation has greater need
for the performance gained from implementing ßoating-point normalization and
denormalization in hardware than a device using a PowerPC embedded controller might.
The PowerPC architecture deÞnes the following features:
¥ Separate 32-entry register Þles for integer instructions. The general-purpose
registers (GPRs) hold source data for integer arithmetic instructions.
¥ Instructions for loading and storing data between the memory system and the GPRs
¥ Uniform-length instructions to allow simpliÞed instruction pipelining and parallel
processing instruction dispatch mechanisms
¥ Nondestructive use of registers for arithmetic instructions in which the second, third,
and sometimes the fourth operand, typically specify source registers for calculations
whose results are typically stored in the target register speciÞed by the Þrst operand.
¥ A precise exception model
¥ A ßexible architecture deÞnition that allows certain features to be performed in
either hardware or with assistance from implementation-speciÞc software
depending on the needs of the processor design
¥ User-level instructions for explicitly storing, ßushing, and invalidating data in the
on-chip caches. The architecture also deÞnes special instructions (cache block touch
instructions) for speculatively loading data before it is needed, reducing the effect of
memory latency.
¥ A memory model that allows weakly-ordered memory accesses. This allows bus
operations to be reordered dynamically, which improves overall performance and in
particular reduces the effect of memory latency on instruction throughput.
¥ Support for separate instruction and data caches (Harvard architecture) and for
uniÞed caches
¥ Support for both big- and little-endian addressing modes
¥ Support for 64-bit addressing. The architecture supports both 32-bit or 64-bit
implementations. This document describes the 32-bit portion of the PowerPC
architecture. For information about the 64-bit architecture, see PowerPC
Microprocessor Family: The Programming Environments.
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