Table of Contents
Advertisement
Part IV. Hardware Interface
Table 13-2 summarizes when active pull-up drivers are enabled as outputs.
Table 13-2. Active Pull-Up Resistors Enabled as Outputs
Signal
TS, BB When the MPC860 is the external bus master throughout the entire bus cycle.
BI
When the MPC860Õs memory controller responds to the access on the external bus, throughout the entire
bus cycle.
TA
When the MPC860Õs memory controller responds to the access on the external bus, then:
¥ For chip selects controlled by a GPCM set for external TA, the MPC860Õs TA buffer is not enabled as an
output.
¥ For chip-selects controlled by the GPCM set to terminate in n wait-states, TA is enabled as an output on
cycle (n-1) and driven high, then is driven low on cycle n, terminating the bus transaction. External logic
can drive TA at any point before this, thus terminating the cycle early. [For example, assume the GPCM is
programmed to drive TA after 15 cycles. If external logic drives TA before 14 clocks have elapsed then the
TA is accepted by the MPC860 as a cycle termination.]
¥ For UPM-controlled chip selects, the TA buffer is enabled as an output throughout the entire bus cycle.
The purpose of active pull-up buffers is to allow access to zero wait-state logic that drives
a shared signal on the clock cycle immediately following a cycle in which the signal is
driven by the MPC860. In other words, it eliminates the need for a bus turn-around cycle.
13.3 Internal Pull-Up and Pull-Down Resistors
The TMS and TRST pins have internal pull-up resistors. MPC860 devices from Rev 0 to
Rev A.3 (masks xE64C and xF84C) have an internal pull-up resistor on TCK/DSCK but no
internal pull-up resistor on TDI/DSDI. This was corrected on Rev B and later; on these
chips, the internal pull-up resistor was removed from TCK/DSCK and an internal pull-up
resistor was added to TDI/DSDI.
If RSTCONF is pulled down, during hardware reset (initiated by HRESET or PORESET),
the data bus D[0Ð31] is pulled down with internal pull-down resistors. These internal
pull-down resistors are to provide a logic-zero default for these pins when programming the
hard reset conÞguration word (See Section 12.3.1.1, ÒHard Reset ConÞguration Word.Ó).
These internal pull-down resistors are disconnected after HRESET is negated.
No other pins have internal pull-ups or pull-downs.
Resistance values for internal pull-up and pull-down resistors are not speciÞed because
their values may vary due to process variations and shrinks in die size, and they are not
tested. Typical values are on the order of 5 KW but can vary by approximately a factor of 2.
13.4 Recommended Basic Pin Connections
The following sections provided recommended pin connections.
13-22
Description
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Advertisement
Table of Contents
