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Branch Type
BC with negative offset
BC with positive offset
BCLR or BCCTR (LR or CTR) address ready
BCLR or BCCTR (LR or CTR) address not ready
B (unconditional branch)
Branch instructions whose condition is unavailable are issued to the reservation station
until they are predicted. Branch instructions that issue with source data already available do
not require prediction (and are said to be resolved). Instructions fetched under a predicted
branch are conditionally fetched. The core ßushes instructions conditionally fetched under
a mispredicted branch.
4.3.3.2 Dispatching Instructions
The sequencer can dispatch a sequential instruction on each clock if the appropriate
execution unit is available and a position is free in the completion queue. The execution unit
must be able to discern whether source data is available and to ensure that no other
executing instruction targets the same destination register. The sequencer informs the
execution units of the existence of the instruction on the instruction bus. The execution units
decode the instruction, check whether the source and destination operands are free, and
inform the sequencer whether instructions can be dispatched.
4.4 Register Set
Registers implemented in the MPC860 core can be grouped as follows:
¥ PowerPC registers. The MPC860 implements the user registers deÞned by the UISA
and VEA portions of the architecture except for those that support ßoating-point
operations. PowerPC registers implemented on the MPC860 are described in
Section 5.1.1, ÒPowerPC RegistersÑUser Registers,Ó and Section 5.1.2, ÒPowerPC
RegistersÑSupervisor Registers.Ó
¥ Implementation-speciÞc registers. These are all special-purpose registers (SPRs).
These are described in Section 5.1.3, ÒMPC860-SpeciÞc SPRs.Ó
4.5 Execution Units
As shown in Figure 4-1, the MPC860 allows parallel execution of instructions using
separate branch processing unit (BPU), load/store unit (LSU), and integer unit (IU). These
execution units are described in the following sections.
MOTOROLA
Table 4-1. Static Branch Prediction
Default Prediction (y=0)
Chapter 4. The PowerPC Core
Part II. PowerPC Microprocessor Module
ModiÞed Prediction (y=1)
Taken
Fall through
Fall through
Wait
Taken
Fall through
Taken
Taken
Wait
Taken
4-9
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