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Address type signals reßect the current status of the master originating the access, not
necessarily the status in which the original access to this location has occurred. An example
of this situation is when a modiÞed data cache block is copied back after the privilege level
of the processor has been changed since the last access to the same cache block. A
functional usage of the address type signal RSV is for the reservation protocol described in
Section 14.4.9, ÒMemory Reservation.Ó Table 14-5 provides the space deÞnition encoded
by the STS, TS, AT[0Ð3], PTR, and RSV.
CPU/
User/
STS TS
CPM
Supervisor
(AT0)
(AT1)
1
x
x
x
0
x
x
x
x
0
0
0
1
1
AT1
MOTOROLA
Table 14-5. Address Types Definition
Reservation/
Instruction/
Program
Data (AT2)
Trace (AT3)
x
x
x
x
0
0
1
1
0
1
0
0
1
1
0
1
AT2
AT3
Chapter 14. MPC860 External Bus Interface
Part IV. Hardware Interface
Program
Reservation
Trace
Address Space DeÞnitions
(RSV)
(PTR)
1
1
No transfer or not the first
transaction of a transfer
x
x
Start of a transaction
0
1
Core-initiated, normal
instruction, program trace,
supervisor mode
1
1
Core-initiated, normal
instruction, supervisor mode
1
0
Core-initiated, reservation
data, supervisor mode
1
1
Core-initiated, normal data,
supervisor mode
0
1
Core-initiated, normal
instruction, program trace,
user mode
1
1
Core-initiated, normal
instruction, user mode
1
0
Core-initiated, reservation
data, user mode
1
1
Core-initiated, normal data,
user mode
1
1
DMA-initiated, normal,
AT[1Ð3] user-programmable
(see IDMA and DMA
function code registers)
14-31
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