Motorola MPC860 PowerQUICC User Manual page 996

Part VI. Debug and Test
Table 37-24. ICR Field Descriptions (Continued)
Bits Name
22Ð2 Ñ Reserved
7
28 LBRK Load/store breakpoint interrupt bit. Set as a result of the assertion of an load/store breakpoint.
Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set.
29 IBRK Instruction breakpoint interrupt bit. Set as a result of the assertion of an instruction breakpoint.
Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set.
30 EBRK External breakpoint interrupt bit (development port, internal or external modules). Set as a
result of the assertion of an external breakpoint. Causes debug mode entry if debug mode is
enabled and the corresponding enable bit is set.
31 DPI Development port interrupt bit. Set by the development port as a result of a debug station
nonmaskable request or when entering debug mode immediately out of reset. Causes debug
mode entry if debug mode is enabled and the corresponding enable bit is set.
37.5.2.2 Debug Enable Register (DER)
The DER, shown in Figure 37-23, lets the user selectively enable events that can cause the
processor to enter debug mode. Its reset value is 0x0200_2000.
Bit 0 1 2
Field Ñ RSTE CHSTPE
Reset 0 0 0
R/W
Bit 16 17 18
Field Ñ SEIE ITLBMSE DTLBMSE ITLBERE DTLBERE
Reset 0 0 1
R/W
SPR
DER protection is described in Table 37-15.
Bits Name
0
1 RSTE
2 CHSTPE
3 MCIE
37-46
3 4 5
MCIE Ñ
0 00
19 20 21
0 0 0
Figure 37-23. Debug Enable Register (DER)
Table 37-25. DER Field Descriptions
Ñ Reserved
Reset interrupt enable bit
0Debug mode entry is disabled (reset value)
1Debug mode entry is enabled
Checkstop enable bit
0 Debug mode entry is disabled
1 Debug mode entry is enabled (reset value)
Machine check interrupt enable bit
0 Debug mode entry is disabled (reset value)
1 Debug mode entry is enabled
MPC860 PowerQUICC UserÕs Manual
Description
6 7 8 9
EXTIE ALIE PRIE FPUVIE DECIE
1 0 0 0
R/W
22 23 24 25
Ñ
00_0000_0
R/W
149
Description
10 11 12 13 14
Ñ SYSIE TRE
0 0_0 0 0
26 27 28 29 30
IBRKE EBRKE DPIE
0 0
MOTOROLA
15
Ñ
0
31
0