Motorola MPC860 PowerQUICC User Manual page 997

Table 37-25. DER Field Descriptions (Continued)
Bits Name
4Ð5
6 EXTIE
7 ALIE
8 PRIE
9 FPUVIE
10 DECIE
11Ð12
13 SYSIE
14 TRE
15Ð16
17 SEIE
18 ITLBMS
19 DTLBMS
20 ITLBER
21 DTLBER
22Ð27
28 LBRKE
29 IBRKE
30 EBRKE
31 DPIE
37.5.2.3 Development Port Data Register (DPDR)
The 32-bit development port data register (DPDR), SPR 630, resides in the development
port logic. It is used for data interchange between the core and the development system. The
DPDR is accessed by using mtspr and mfspr and implemented using a special bus cycle
on the internal bus. See Section 37.3.2.2.1, ÒDevelopment Port Shift Register.Ó
MOTOROLA
Ñ Reserved
External interrupt enable bit
Alignment interrupt enable bit
Program interrupt enable bit
Floating-point unavailable interrupt enable bit
Decrementer interrupt enable bit
Ñ Reserved
System call interrupt enable bit
Trace interrupt enable bit
0 Debug mode entry is disabled
1 Debug mode entry is enabled (reset value)
Ñ Reserved
Software emulation interrupt enable bit
0 Debug mode entry is disabled (reset value)
1 Debug mode entry is enabled
Implementation-speciÞc ITLB miss enable bit
E
Implementation-speciÞc DTLB miss enable bit
E
Implementation-speciÞc ITLB error enable bit
E
Implementation-speciÞc DTLB error enable bit
E
Ñ Reserved
Load/store breakpoint interrupt enable bit
0 Debug mode entry is disabled
1 Debug mode entry is enabled (reset value)
Instruction breakpoint interrupt enable bit
External breakpoint interrupt enable bit
Development port nonmaskable request enable bit
Chapter 37. System Development and Debugging
Description
Part VI. Debug and Test
37-47