Motorola MPC860 PowerQUICC User Manual page 468

Part IV. Hardware Interface
Table 16-15. GPL_X5 Signal Behavior (Continued)
Controlling Machine
Memory Slave Access
Access Clock Cycle
UPMB First
Second,
third...
16.6.4.5 Loop Control (LOOP)
The LOOP bit in the RAM word (bit 24) speciÞes the beginning and end of a set of UPM
RAM words that are to be repeated. The Þrst time LOOP = 1, the memory controller
recognizes it as a loop start word and loads the memory loop counter with the
corresponding contents of the loop Þeld shown in Table 16-16. The next RAM word for
which LOOP = 1 is recognized as a loop end word. When it is reached, the loop counter is
decremented by one.
Continued loop execution depends on the loop counter. If the counter is not zero, the next
RAM word executed is the loop start word. Otherwise, the next RAM word executed is the
one after the loop end word. Loops can be executed sequentially but cannot be nested.
16-42
ORx RAM Word
G5LA G5LS G5T4 G5T3
0 0 x x
1
1 0 x x
1
0 x 0 x
1 x
x 0
x 1
1 x 0 x
1 x
x 0
x 1
MPC860 PowerQUICC UserÕs Manual
GPL_X5 Behavior at the Controlling Clock Edge
GPL_B5 is driven low at the falling edge of GCLK1_50.
GPL_B5 is driven high at the falling edge of GCLK1_50.
GPL_A5 is driven low at the falling edge of GCLK1_50.
GPL_A5 is driven high at the falling edge of GCLK1_50.
GPL_B5 is driven low at the falling edge of GCLK2_50 in
the current UPM cycle.
GPL_B5 is driven high at the falling edge of GCLK2_50 in
the current UPM cycle.
GPL_B5 is driven low at the falling edge of GCLK1_50 in
the current UPM cycle.
GPL_B5 is driven high at the falling edge of GCLK1_50 in
the current UPM cycle.
GPL_A5 is driven low at the falling edge of GCLK2_50 in
the current UPM cycle.
GPL_A5 is driven high at the falling edge of GCLK2_50 in
the current UPM cycle.
GPL_A5 is driven low at the falling edge of GCLK1_50 in
the current UPM cycle.
GPL_A5 is driven high at the falling edge of GCLK1_50 in
the current UPM cycle.
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