The Powerpc Core; Powerpc Architecture Overview - Motorola MPC860 PowerQUICC User Manual

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Chapter 4

The PowerPC Core

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The core implements all PowerPC user-level instructions deÞned for 32-bit
implementations except ßoating-point instructions (load/store and arithmetic). Likewise, it
supports the registers deÞned by the PowerPC architecture necessary for the supported
instructions.
The MPC860 core adheres to portions of the PowerPC architecture deÞnition for supervisor
operations. For example, it implements the PowerPC exception model (excluding
inappropriate exceptions, such as those that support ßoating-point operations). The
architecture-deÞned memory management model has been modiÞed to suit the speciÞc
needs of the MPC860 core. Additional exceptions are deÞned (as permitted by the
architecture) to support address translation.
The PowerPC architecture deÞnes features not supported on the MPC860 hardware. These
features include support for 64-bit addressing, multiprocessing, ßoating-point arithmetic,
and some memory management features.
The core also implements MPC860-speciÞc development support features such as
breakpoint and watchpoint mechanisms, program-ßow tracking data generation, and debug
mode operation.
This chapter describes the functional speciÞcations of the core. It is based on the PowerPC
Microprocessor Family: The Programming Environments for 32-Bit Microprocessors,
which provides a more in-depth discussion of issues related to the 32-bit portion of the
PowerPC architecture.
The subset of PowerPC instructions supported by the MPC860 are listed in Chapter 6,
ÒMPC860 Instruction Set.Ó

4.1 PowerPC Architecture Overview

The PowerPC architecture, developed jointly by Motorola, IBM, and Apple Computer, is
based on the POWERª architecture implemented by RS/6000ª family of computers. The
PowerPC architecture takes advantage of recent technological advances in such areas as
process technology, compiler design, and reduced instruction set computing (RISC)
microprocessor design to provide software compatibility across a diverse family of
implementations, primarily single-chip microprocessors, intended for a wide range of
MOTOROLA
Chapter 4. The PowerPC Core
4-1

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