Unaligned Accesses; Atomic Update Primitives - Motorola MPC860 PowerQUICC User Manual

The nonspeculative identiÞcation relates to the state of the cycleÕs associated instruction.
For lmw, although the accesses are pipelined into the bus, they are all marked as
nonspeculative because the instruction is nonspeculative. If a single-register load
instruction generates more than one bus cycle, some of the cycles can be marked as
speculative and later cycles can be marked as nonspeculative after all prior instructions end.
Speculative load accesses to external memory marked nonspeculative cannot occur until the
load instruction becomes nonspeculative.

4.5.3.5 Unaligned Accesses

Although the 32-bit U-bus supports only naturally aligned transfers, the LSU supports
unaligned accesses in hardware by breaking them into a pipelined series of aligned
transfers. Table 4-2 shows the number of bus cycles needed for single-register load/store
accesses.
Table 4-2. Bus Cycles Needed for Single-Register Load/Store Accesses
Transfer Size Transfer Address (Last Two Bits)
Byte
Half Word
Word

4.5.3.6 Atomic Update Primitives

The lwarx and stwcx. instructions are atomic update primitives and are used to set and clear
memory reservations. Reservation accesses made by the same processor are implemented
by the LSU. The external bus interface implements memory reservations as they relate to
accesses made by external bus devices. Accesses made by other internal devices to internal
memories implement memory reservations as they relate to special internal bus snoop logic.
MOTOROLA
Number of Bus Cycles
0x00
0x01
0x02
0x03
0x00
0x01
0x02
0x03
0x00
0x01
0x02
0x03
Chapter 4. The PowerPC Core
Part II. PowerPC Microprocessor Module
Transfer Type Address/Size
1 Aligned
1 Aligned
1 Aligned
1 Aligned
1 Aligned
2 Unaligned
1 Aligned
2 Unaligned
1 Aligned
3 Unaligned
2 Unaligned
3 Unaligned
0x00/byte
0x01/byte
0x02/byte
0x03/byte
0x00/halfword
0x01/byte
0x02/byte
0x02/halfword
0x03/byte
0x04/byte
0x00/word
0x01/byte
0x02/halfword
0x05/byte
0x02/halfword
0x04/halfword
0x03/byte
0x04/halfword
0x06/byte
4-13