Motorola MPC860 PowerQUICC User Manual page 301

11.10 The Real-Time Clock
The real-time clock is a 45-bit counter, clocked by PITRTCLK, to provide time-of-day to
the operating system and application software. The counter is not affected by HRESET,
SRESET, or PORESET and operates in all low-power modes. It must be initialized by
software. The real-time clock can be programmed to generate a maskable interrupt when
the time value matches the value programmed in the associated alarm register. It can also
be programmed to generate an interrupt once each second. A control and status register is
used to selectively enable or disable functions and report the interrupt source. The real-time
clock registers (RTCSC, RTC, RTSEC, and RTCAL) can be protected (locked) from
accidental writes after PORESET through the use of key registers (RTCSCK, RTCK,
RTSECK, and RTCALK), which are described in Section 11.4.5, ÒRegister Lock
Mechanism.Ó To unlock a register, write the key word 0x55CC_AA33 to the key registers.
Note that the real-time clock will count in seconds only if PITRTCLK is supplied by a
32.768 kHz or 38.4 kHz source.
FRZ
Clock
PITRTCLK
Disable
Clock
Figure 11-23. Real-Time Clock Block Diagram
11.10.1 Real-Time Clock Status and Control Register (RTCSC)
The real-time clock status and control register (RTCSC) is used to enable the different
real-time clock functions and for reporting interrupt sources. Status bits are cleared by
writing a ones (writing a zero has no effect). This register can be read at any time. Note that
RTCSC is a keyed register. It must be unlocked in RTCSCK before it can be written.
Bit 0 1 2
Field
Reset
R/W
Addr
Figure 11-24. Real-Time Clock Status and Control Register (RTCSC)
Table 11-20 describes RTCSC Þelds.
MOTOROLA
RTSEC
Divide
by 8,192
Divide
by 9,600
3 4 5 6
RTCIRQ
0000_0000
(IMMR & 0xFFFF0000) + 0x220
Chapter 11. System Interface Unit
32-Bit Counter
MUX
32-Bit Register
38K
7 8 9 10 11
SEC ALR Ñ 38K
0 0 0 Ñ
R/W
Part III. Configuration
SEC
Interrupt
Alarm
=
Interrupt
12 13 14 15
SIE ALE RTF RTE
0 0 0 Ñ
11-27