Motorola MPC860 PowerQUICC User Manual page 361

CLKOUT
BR
BG
BB
A[0Ð31]
R/W
TSIZ[0Ð1], AT[0Ð3]
BURST
TS
Data
TA
Figure 14-6. Basic Timing: Single-Beat Read Cycle, One Wait State
14.4.2.2 Single-Beat Write Flow
The basic write cycle begins with a bus arbitration, followed by the address transfer, then
the data transfer. The following ßow and timing diagrams show the handshakes as
applicable to the Þxed transaction protocol.
MOTOROLA
Receive BG and BB negated
Assert BB, drive address and assert TS
Wait State
Chapter 14. MPC860 External Bus Interface
Part IV. Hardware Interface
Data is Valid
14-9