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Bit
0
1
Field
Reset
R/W
Addr
(IMMR & FFFF0000) + 0x104 (OR0), 0x10C (OR1), 0x114 (OR2), 0x11C (OR3), 0x124 (OR4), 0x12C
Bit
16
17 18 19
Field
AM
ATM
Reset
R/W
Addr
OR0 has separate default values and is read-only, as shown in Figure 16-7.
Bit
0
1
Field
Reset
R/W
Addr
(IMMR & FFFF0000) + 0x104 (OR0), 0x10C (OR1), 0x114 (OR2), 0x11C (OR3), 0x124 (OR4), 0x12C
Bit
16
17 18 19
Field
AM
ATM
Reset
0
0
R/W
Addr
MOTOROLA
2
3
4
5
6
0000_0000_0000_0000
(OR5), 0x134 (OR6), 0x13C (OR7)
20
21
CSNT/SAM ACS/G5LA,G5LS BIH
0000_0000_0000_0000
(IMMR & FFFF0000) + 0x106
Figure 16-7. Option Registers (ORx)
2
3
4
5
6
0000_0000_0000_0000
(OR5), 0x134 (OR6), 0x13C (OR7)
20
21
CSNT/SAM ACS/G5LA,G5LS BIH
1
11
OR0: R; R/W for all others
(IMMR & FFFF0000) + 0x106
Figure 16-8. OR0 Reset Defaults
Chapter 16. Memory Controller
7
8
9
10
AM
R/W
22
23
24 25 26 27
SCY
R/W
7
8
9
10
AM
R
22
23
24 25 26 27
SCY
1
1111
Part IV. Hardware Interface
11
12
13
14
28
29
30
SETA TRLX EHTR
11
12
13
14
28
29
30
SETA TRLX EHTR
0
1
0
16-11
15
31
Ñ
15
31
Ñ
0
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