Motorola MPC860 PowerQUICC User Manual page 519

Table 17-13. POR Field Descriptions (Continued)
Bits Name
16Ð19 PSST PCMCIA strobe set up time (address to strobe assertion). SpeciÞes when IOWR_B or WE_B are
asserted during a PCMCIA write access or when IORD_B or OE_B are asserted during a PCMCIA
read access handled by the PCMCIA interface. This helps meet address/setup time requirements for
slow memories and peripherals.
0000 Reserved
0001 Address to strobe assertion 1 clock cycle
0010 Address to strobe assertion 2 clock cycles
...
1111 Address to strobe assertion 15 clock cycles
20Ð24 PSL PCMCIA strobe length. Determines the number of cycles the strobe is asserted during a PCMCIA
access for this window and, thus, it is the main parameter for determining cycle length. The cycle may
be lengthened by asserting WAIT.
00001 Strobe asserted 1 clock cycles
00010 Strobe asserted 2 clock cycles
...
11111 Strobe asserted 31 clock cycles
00000 Strobe asserted 32 clock cycles
25 PPS PCMCIA port size. SpeciÞes the port size of this PCMCIA window.
0 8 bits port size
1 16 bits port size
26Ð28 PRS PCMCIA region select.
000 Common memory space
001 Reserved
010 Attribute memory space
011 I/O space
100 DMA (normal DMA transfer)
101 DMA last transaction
11x Reserved
Note: The DMA encoding generates a normal DMA transfer unless signaled as last by the on-chip
DMA controller. In this case TC(OE) or TC (WE) is asserted.The DMA last transaction encoding
generates a DMA transfer with TC(OE) or TC (WE) asserted, regardless of any internal indication.
29 PSLOT PCMCIA slot identiÞer.
0 This window deÞned for slot A.
1 This window deÞned for slot B.
30 WP Write-protect enable.
0 Not write protected.
1 Write protected. Attempting to write to this window causes a machine check interrupt.
31 PV PCMCIA valid. Indicates whether the contents of the OBR and POR pair are valid.
0This bank is invalid.
1This bank is valid.
MOTOROLA
Description
Chapter 17. PCMCIA Interface
Part IV. Hardware Interface
17-15