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Part II. PowerPC Microprocessor Module
ÒSystem Reset Interrupt (0x00100),Ó describes values for these registers after system reset.
When a hard or soft reset occurs, registers are set in the same way, as follows:
¥ SRR0, SRR1ÑSet to an undeÞned value.
¥ MSR[IP]ÑProgrammable through the IIP bit in the hard reset conÞguration word.
¥ MSR[ME]ÑCleared.
¥ ICTRLÑCleared.
¥ LCTRL1ÑCleared.
¥ LCTRL2ÑCleared.
¥ COUNTA[16Ð31]ÑCleared.
¥ COUNTB[16Ð31]ÑCleared.
¥ ICRÑCleared (no exception occurred).
¥ DER[2,14,28Ð31]ÑSet (all debug-speciÞc exceptions cause debug mode entry).
Reset values for memory-mapped registers are provided with individual register
descriptions throughout this manual.
5-12
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
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