Motorola MPC860 PowerQUICC User Manual page 902

Part V. The Communications Processor Module
Bit 0 1
Field Ñ
Reset
R/W
Addr
Figure 34-18. Port D Pin Assignment Register (PDPAR)
Table 34-20 describes PDPAR bits.
Bits Name
0Ð2 Ñ Reserved and must be cleared. Note that setting bits 0 or 1 causes erratic behavior resulting in
CPM lockup. (These bits apply only for the MPC860SAR.)
3Ð15 DDn ConÞgures a signal for general-purpose I/O or for dedicated peripheral function
0 General-purpose I/O. The peripheral functions of the signal are not used.
1 Dedicated peripheral function. The signal is used by the internal module. The on-chip
peripheral function to which it is dedicated can be determined by other bits.
34-20
2 3 4 5 6
0000_0000_0000_0000
Table 34-20. PDPAR Bit Descriptions
MPC860 PowerQUICC UserÕs Manual
7 8 9 10 11
DD3ÐDD15
R/W
0x972
Description
12 13 14 15
MOTOROLA