Motorola MPC860 PowerQUICC User Manual page 615

Table 21-9 describes SIRP Þelds.
Bits Name
0Ð1, 8Ð9, Ñ
16Ð17, 24Ð25
2, 10, 18, 26 VRn,
VTn
3-7, 11Ð15, RnPTR,
19Ð23, 27Ð31 TnPTR
Table 21-10 describes the pointer values as affected by SIGMR[RDM].
RDM
00 RaPTR/TaPTR point to the Þrst 32 entries and RbPTR/TbPTR point to the second 32 entries.
RaPTR/RbPTR and TaPTR/TbPTR point to the active Rx and Tx entries, respectively. When the SI services
entries 1Ð32, RaPTR/TaPTR is incremented and RbPTR/TbPTR is continuously cleared. Conversely, when the
SI services entries 33Ð64, RaPTR/TaPTR is continuously cleared and RbPTR/TbPTR is incremented.
01 For the receiver, whether RaPTR or RbPTR is used depends on which portion of the SI Rx RAM is active (V-bit
set). Whether TaPTR or TbPTR is used depends on which portion of the Tx RAM is active.
¥ If VRa = 1, RaPTR points to the active RXa entry. The Rx address block is 0Ð127; SISTR[CRORa] = 0.
¥ If VRb = 1, RbPTR points to the active RXa entry. The Rx address block is 128Ð255; SISTR[CRORa] = 1.
¥ If VTa = 1, TaPTR points to the active TXa entry. The Tx address block is 256Ð383; SISTR[CROTa] = 0.
¥ If VTb = 1, TbPTR points to the active TXa entry. The Tx address block is 384Ð511; SISTR[CROTa] = 1.
10 The simplest conÞgurationÑeach pointer is used continuously and has only one function.
RaPTR points to the active RXa entry and RbPTR points to the active RXb entry.
TaPTR points to the active TXa entry and TbPTR points to the active TXb entry.
11 Each pointer is used continuously. The section of SI RAM it points to depends on whether its value is in the Þrst
half (0Ð15) or the second half (16Ð31).
¥ RaPTR points to the active RXa entry. If RaPTR = 0Ð15, the current-route RAM is SI RAM address block
0Ð63 and SISTR[CRORa] = 0. If RaPTR = 16Ð31, the current-route RAM is SI RAM address block 64Ð127
and SISTR[CRORa] = 1.
¥ RbPTR points to the active RXb entry. If RbPTR = 0Ð15, the current-route RAM is SI RAM address block
128Ð191 and SISTR[CRORb] = 0. If RbPTR = 16Ð31, the current-route RAM is SI RAM address block
192Ð255 and SISTR[CRORb] = 1.
¥ TaPTR points to the active TXa entry. If TaPTR = 0Ð15, the current-route RAM is SI RAM address block
256Ð319 and SISTR[CROTa] = 0. If TaPTR = 16Ð31, the current-route RAM is SI RAM address block
320Ð383 and SISTR[CROTa] = 1.
¥ TbPTR points to the active TXb entry. If TbPTR = 0Ð15, the current-route RAM is SI RAM address block
384Ð447 and SISTR[CROTb] = 0. If TbPTR = 16Ð31, the current-route RAM is SI RAM address block
448Ð511 and SISTR[CROTb] = 1.
MOTOROLA
Table 21-9. SIRP Field Descriptions
Reserved, should be cleared.
Valid if set. Knowing whether an entry is valid (active) helps when the PTR value is zero.
The V bits eliminate having to read both SIRP and SISTR.
Transmit/receive SI RAM entry pointers. Incremented by one for each entry processed.
These 5-bit pointersÕ values range from 0Ð31, corresponding to 32 SI RAM entries,
although the entire range may not be used. For instance, if SIRAM[LST] is set in the Þfth
entry, the pointer reßects values 0Ð4. When the SI processes the Þfth, the pointer returns
to 0. Pointer values are described in Table 21-10, and are based on SIGMR[RDM].
Table 21-10. SIRP Pointer Values
Chapter 21. Serial Interface
Part V. The Communications Processor Module
Description
ConÞguration
21-27