Motorola MPC860 PowerQUICC User Manual page 412

Part IV. Hardware Interface
15.4.2 Internal Logic Power (VDDL)
The internal logic can be fed by the same 3.3V source which powers VDDH. VDDL is
identiÞed as a separate power supply only to facilitate power measurements.
15.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1)
To improve stability, the power supply pins for the SPLL are uniquely identiÞed in order to
allow special Þltration to be provided for them.
A well-regulated voltage should be applied to VDDSYN via a low impedance path to the
VDDH/VDDL power rail. The allowable noise on the VDDSYN power plane is 20 mV
peak up to a bandwidth of 100 MHz. This typically requires isolation of the VDDSYN
power plane from the VDDH/VDDL power plane. An example implementation of this is a
split power plane, with the VDDSYN plane implemented as an island in the VDDH/VDDL
power plane, connected to the VDDH/VDDL power plane with an inductor and to the
ground plane with bypass capacitors. An inductor value of 8.2 mH and bypass capacitor
values of 0.1 mF and 10 mF provide a two-pole Þlter with a cutoff frequency of 500 Hz.
VSSSYN and VSSSYN1 must have a low impedance path to the ground plane. If sufÞcient
isolation is provided for VDDSYN (as described above), no additional isolation for
VSSSYN and VSSSYN1 is required.
15.4.4 Keep-Alive Power (KAPWR)
The OSCM, timebase, decrementer, periodic interrupt timer, real-time clock, SCCR,
PLPRCR, and RSR are all connected to the keep-alive power (KAPWR) rail. This power
rail architecture allows the system to remove the power at the VDDH/VDDL/VDDSYN
pins during power-down mode.
When VDDH is active, the internal modules connected to KAPWR are instead powered by
VDDH. KAPWR is only used for this function when power at VDDH is shut off. This
operation conserves the power of the KAPWR supply.
15.5 Power Control (Low-Power Modes)
To optimize power consumption, the MPC860 provides low-power modes that can be used
to dynamically activate and deactivate certain internal modules, such that only the needed
modules are operating at any given time. In addition to normal high mode (i.e. fully
activated), the MPC860 supports normal low, doze high, doze low, sleep, deep-sleep, and
power-down modes.
In addition to these power-saving modes, it should be noted that the architecture of the CPM
inherently supports optimum power consumption. When the CPM is idle, it uses its own
power-saving mechanism to shut down automatically.
Low-power modes are controlled in the PLPRCR[LPM] and PLPRCR[CSRC]. Events can
cause automatic changes from one low-power mode to another. These events include
15-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA