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MC9S12DJ256
Motorola MC9S12DJ256 Manuals
Manuals and User Guides for Motorola MC9S12DJ256. We have
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Motorola MC9S12DJ256 manual available for free PDF download: User Manual
Motorola MC9S12DJ256 User Manual (132 pages)
Brand:
Motorola
| Category:
Microcontrollers
| Size: 0.85 MB
Table of Contents
Table of Contents
5
Figure 0-1 Order Partnumber Example
15
Table 0-1 Derivative Differences
15
Table 0-2 Document References
17
Table 0-3 Specification Change Summary for Maskset L91N
17
Section 1 Introductionmc9S12Dt256
19
Overview
19
Features
19
Modes of Operation
21
Block Diagram
22
Figure 1-1 MC9S12DT256 Block Diagram
23
Device Memory Map
24
Table 1-1 Device Memory Map
24
Figure 1-2 MC9S12DT256 Memory Map
26
Detailed Register Map
27
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
43
Part ID Assignments
50
Table 1-3 Assigned Part ID Numbers
50
Table 1-4 Memory Size Registers
50
Section 2 Signal Description
51
Device Pinout
51
Figure 2-1 Pin Assignments in 112-Pin LQFP
52
Signal Properties Summary
53
Figure 2-2 Pin Assignments in 80-Pin QFP for MC9S12DJ256
53
Table 2-1 Signal Properties
53
Detailed Signal Descriptions
56
EXTAL, XTAL - Oscillator Pins
56
RESET - External Reset Pin
56
TEST - Test Pin
57
VREGEN - Voltage Regulator Enable Pin
57
XFC - PLL Loop Filter Pin
57
BKGD / TAGHI / MODC - Background Debug, Tag High, and Mode Pin
57
PAD15 / AN15 / ETRIG1 - Port AD Input Pin of ATD1
57
PAD[14:08] / AN[14:08] - Port AD Input Pins of ATD1
57
Figure 2-3 PLL Loop Filter Connections
57
PAD7 / AN07 / ETRIG0 - Port AD Input Pin of ATD0
58
PAD[06:00] / AN[06:00] - Port AD Input Pins of ATD0
58
PA[7:0] / ADDR[15:8] / DATA[15:8] - Port a I/O Pins
58
PB[7:0] / ADDR[7:0] / DATA[7:0] - Port B I/O Pins
58
PE7 / NOACC / XCLKS - Port E I/O Pin 7
58
Figure 2-4 Colpitts Oscillator Connections (PE7=1)
59
Figure 2-5 Pierce Oscillator Connections (PE7=0)
59
PE6 / MODB / IPIPE1 - Port E I/O Pin 6
60
PE5 / MODA / IPIPE0 - Port E I/O Pin 5
60
PE4 / ECLK - Port E I/O Pin 4
60
PE3 / LSTRB / TAGLO - Port E I/O Pin 3
60
Figure 2-6 External Clock Connections (PE7=0)
60
PE2 / R/W - Port E I/O Pin 2
61
PE1 / IRQ - Port E Input Pin 1
61
PE0 / XIRQ - Port E Input Pin 0
61
PH7 / KWH7 / SS2 - Port H I/O Pin 7
61
PH6 / KWH6 / SCK2 - Port H I/O Pin 6
61
PH5 / KWH5 / MOSI2 - Port H I/O Pin 5
61
PH4 / KWH4 / MISO2 - Port H I/O Pin 2
61
PH3 / KWH3 / SS1 - Port H I/O Pin 3
61
PH2 / KWH2 / SCK1 - Port H I/O Pin 2
62
PH0 / KWH0 / MISO1 - Port H I/O Pin 0
62
PJ7 / KWJ7 / TXCAN4 / SCL - PORT J I/O Pin 7
62
PJ6 / KWJ6 / RXCAN4 / SDA - PORT J I/O Pin 6
62
PJ[1:0] / KWJ[1:0] - Port J I/O Pins [1:0]
62
PK7 / ECS / ROMONE - Port K I/O Pin 7
62
PK[5:0] / XADDR[19:14] - Port K I/O Pins [5:0]
63
PM7 / TXCAN4 - Port M I/O Pin 7
63
PM6 / RXCAN4 - Port M I/O Pin 6
63
PM5 / TXCAN0 / TXCAN4 / SCK0 - Port M I/O Pin 5
63
PM3 / TXCAN1 / TXCAN0 / SS0 - Port M I/O Pin 3
63
PM2 / RXCAN1 / RXCAN0 / MISO0 - Port M I/O Pin 2
63
PM1 / TXCAN0 / TXB — Port M I/O Pin 1
64
PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
65
PS0 / RXD0 - Port S I/O Pin 0
66
PT[7:0] / IOC[7:0] - Port T I/O Pins [7:0]
66
Power Supply Pins
66
VDDX,VSSX - Power & Ground Pins for I/O Drivers
66
VDDR, VSSR - Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
66
PS2 / RXD1 — Port S I/O Pin 2
66
VDD1, VDD2, VSS1, VSS2 - Core Power Pins
67
VDDA, VSSA - Power Supply Pins for ATD and VREG
67
VRH, VRL - ATD Reference Voltage Input Pins
67
VDDPLL, VSSPLL - Power Supply Pins for PLL
67
Table 2-2 MC9S12DP256 Power and Ground Connection Summary
67
VREGEN - on Chip Voltage Regulator Enable
68
Section 3 System Clock Description
69
Overview
69
Figure 3-1 Clock Connections
69
Section 4 Modes of Operation
71
Overview
71
Chip Configuration Summary
71
Table 4-1 Mode Selection
71
Table 4-2 Clock Selection Based on PE7
71
Security
72
Securing the Microcontroller
72
Operation of the Secured Microcontroller
72
Table 4-3 Voltage Regulator VREGEN
72
Unsecuring the Microcontroller
73
Low Power Modes
73
Stop
73
Pseudo Stop
73
Wait
73
Run
74
Section 5 Resets and Interrupts
75
Overview
75
Vectors
75
Vector Table
75
Table 5-1 Interrupt Vector Locations
75
Effects of Reset
77
I/O Pins
77
Memory
77
CPU12 Block Description
79
HCS12 Breakpoint (BKP) Block Description
80
Figure 20-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator
84
Figure 20-2 Recommended PCB Layout for 80QFP Colpitts Oscillator
85
Figure 20-3 Recommended PCB Layout for 112LQFP Pierce Oscillator
86
Figure 20-4 Recommended PCB Layout for 80QFP Pierce Oscillator
87
Appendix A Electrical Characteristics
89
General
89
Parameter Classification
89
Power Supply
89
A.1 General
89
Pins
90
A.1.3 Pins
90
Current Injection
91
Absolute Maximum Ratings
91
Table A-1 Absolute Maximum Ratings
91
A.1.4 Current Injection
91
ESD Protection and Latch-Up Immunity
92
Table A-2 ESD and Latch-Up Test Conditions
92
Table A-3 ESD and Latch-Up Protection Characteristics
92
Operating Conditions
93
Power Dissipation and Thermal Characteristics
93
Table A-4 Operating Conditions
93
A.1.7 Operating Conditions
93
I/O Characteristics
95
A.1.9 I/O Characteristics
95
Table A-5 Thermal Package Characteristics
95
Table A-6 5V I/O Characteristics
96
Supply Currents
97
A.1.10 Supply Currents
97
Table A-7 Supply Current Characteristics
98
ATD Characteristics
99
ATD Operating Characteristics
99
Factors Influencing Accuracy
99
A.2 ATD Characteristics
99
Table A-8 ATD Operating Characteristics
99
Table A-9 ATD Electrical Characteristics
100
ATD Accuracy
101
Table A-10 ATD Conversion Performance
101
A.2.3 ATD Accuracy
101
Figure A-1 ATD Accuracy Definitions
102
NVM, Flash and EEPROM
103
NVM Timing
103
Table A-11 NVM Timing Characteristics
104
NVM Reliability
106
Table A-12 NVM Reliability Characteristics
106
A.3.2 NVM Reliability
106
Figure A-2 Typical Endurance Vs Temperature
107
Voltage Regulator
109
Table A-13 Voltage Regulator Recommended Load Capacitances
109
A.4 Voltage Regulator
109
Reset, Oscillator and PLL
111
Startup
111
Table A-14 Startup Characteristics
111
Oscillator
112
Table A-15 Oscillator Characteristics
112
A.5.2 Oscillator
112
Phase Locked Loop
113
Figure A-3 Basic PLL Functional Diagram
113
Figure A-4 Jitter Definitions
115
Figure A-5 Maximum Bus Clock Jitter Approximation
115
Table A-16 PLL Characteristics
116
Mscan
117
Table A-17 MSCAN Wake-Up Pulse Characteristics
117
A.6 Mscan
117
Spi
119
Master Mode
119
A.7.1 Master Mode
119
Figure A-6 SPI Master Timing (CPHA=0)
119
Table A-18 Measurement Conditions
119
Figure A-7 SPI Master Timing (CPHA=1)
120
Table A-19 SPI Master Mode Timing Characteristics
120
Slave Mode
121
A.7.2 Slave Mode
121
Figure A-8 SPI Slave Timing (CPHA=0)
121
Figure A-9 SPI Slave Timing (CPHA=1)
122
Table A-20 SPI Slave Mode Timing Characteristics
122
External Bus Timing
123
General Muxed Bus Timing
123
Figure A-10 General External Bus Timing
124
Appendix B Package Information
127
General
127
B.1 General
127
112-Pin LQFP Package
128
Figure B-1 112-Pin LQFP Mechanical Dimensions (Case No. 987)
128
80-Pin QFP Package
129
Figure B-2 80-Pin QFP Mechanical Dimensions (Case No. 841B)
129
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