Motorola MPC860 PowerQUICC User Manual page 149

Table 5-10. MPC860-Specific Debug-Level SPRs (Continued)
SPR Number
Decimal SPR[5Ð9] SPR[0Ð4]
152 00100 11000
153 00100 11001
154 00100 11010
155 00100 11011
156 00100 11100
157 00100 11101
158 00100 11110
159 00100 11111
630 10011 10110
5.1.3.1 Accessing SPRs
All SPRs are accessed using the mtspr and mfspr instructions, regardless of whether they
are within the processor core. To access registers outside of the core, an internal bus tenure
occurs using the address lines as described in Table 5-11.
Table 5-11. Addresses of SPRs Located Outside of the Core
Address errors in this tenure cause a software emulation exception.
5.2 Register Initialization at Reset
This section describes how basic registers are set under reset conditions, other register
settings are described in Chapter 8, ÒInstruction and Data Caches,Ó and Chapter 9,
ÒMemory Management Unit (MMU).Ó
A system reset interrupt occurs when a nonmaskable interrupt is generated either by the
software watchdog timer or the assertion of IRQ0. The only registers affected by the system
reset interrupt are MSR, SRR0, and SRR1; no other reset activity occurs. Section 7.1.2.1,
MOTOROLA
Name
CMPE
CMPF
CMPG
CMPH
LCTRL1
LCTRL2
ICTRL
BAR
DPDR
Address Lines
0Ð17 18Ð22
0...0 SPR[0Ð4]
Chapter 5. PowerPC Core Register Set
Part II. PowerPC Microprocessor Module
Serialize Access
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Fetch sync on write
Write: Fetch sync
Read: Sync relative to load/store operations. See
Section 5.1.2.1, ÒDAR, DSISR, and BAR Operation.Ó
Read and Write
23Ð27 28Ð31
SPR[5Ð9] 0000
5-11