Motorola MPC860 PowerQUICC User Manual page 975

Part VI. Debug and Test
37.3.1.5 Saving Machine State when Entering Debug Mode
If any load/store-type exception causes the store to enter debug mode, the critical
information in DAR and DSISR must be saved before any other operation is performed.
Failing to do so can cause information loss if the development software encounters another
load/store-type exception. Because exceptions are treated differently in debug mode, there
is no need to save SRR0 and SRR1.
37.3.1.6 Running in Debug Mode
When running in debug mode, all fetch cycles access the development port, regardless of
the cycleÕs actual address. All load/store cycles access the real memory system according
to the cycleÕs address. The data register of the development port is mapped as an SPR and
is accessed using mtspr and mfspr via special load/store cycles (see Table 37-14).
Exceptions are treated differently in debug mode; the ICR is updated on recognition of an
exception according to the event that caused it. A special error indication (ICR_OR) is
asserted for one clock cycle to notify the development port when an exception occurs.
Execution continues in debug mode without changing SRR0 and SRR1. To allow the
development system to detect the excepting instruction, ICR_OR is asserted before the next
fetch. Not all exceptions are recognized in debug mode. Hardware does not generate
breakpoints and watchpoints in debug mode, regardless of the value of MSR[RI]. On
entering debug mode, MSR[EE] is cleared, forcing hardware to ignore external and
decrementer interrupts.
Note that debug software must not set MSR[EE] in debug mode because the external
interrupt event is a level signal. Because the core only reports and does not handle
exceptions in debug mode, core hardware does not clear MSR[EE]. This event, if enabled,
is recognized on every clock. When ICR_OR is asserted the development station should
read the ICR to Þnd what event caused the exception. Because SRR0 and SRR1 do not
change, if an exception is recognized in debug mode, they change only once when entering
debug mode. However, saving SRR0 and SRR1 when entering debug mode is unnecessary.
37.3.1.7 Exiting Debug Mode
The rÞ instruction is used to exit from debug mode to return to the normal processor
operation and to negate the freeze indication. The development system may monitor the
FRZ or FLS pins to make sure the MPC860 is out of debug mode. It is the responsibility of
the debugger to read the ICR before performing the rÞ instruction. Failing to do so forces
the core to immediately reenter debug mode and to reassert the freeze indication if an
asserted ICR bit has a corresponding enable bit set in the DER.
37.3.2 Development Port Communication
The development port provides a full duplex serial interface for communications between
the internal development support logic and an external development tool. Figure 37-5
shows the relationship of the development support logic to the rest of the core. For clarity,
the development port support logic is shown as a separate block.
MOTOROLA Chapter 37. System Development and Debugging 37-25