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Bits
Name
11
LCW
Late collision window.
0 A late collision is any collision that occurs at least 64 bytes from the preamble.
1 A late collision is any collision that occurs at least 56 bytes from the preamble.
12Ð14 NIB
Number of ignored bits. Determines how soon after RENA assertion the Ethernet controller should
begin looking for the start frame delimiter. Typically NIB = 101 (22 bits).
000Begin searching 13 bits after the assertion of RENA.
001Begin searching 14 bits after the assertion of RENA.
...
111Begin searching 24 bits after the assertion of RENA.
15
FDE
Full duplex Ethernet.
0 Disable full-duplex Ethernet mode.
1 Enable full-duplex Ethernet mode.
Note: When FDE = 1, PSMR[LPB] must be set also.
28.19 SCC Ethernet Receive BD
The Ethernet controller uses the RxBD to report on the received data for each buffer.
0
1
Offset + 0
E
Ñ
Offset + 2
Offset + 4
Offset + 6
Table 28-7 describes RxBD status and control Þelds.
Table 28-7. SCC Ethernet Receive RxBD Status and Control Field Descriptions
Bits Name
0
E
Empty.
0 The buffer is full or stopped receiving data because an error occurred. The core can read or write any
Þelds of this RxBD. The CPM does not use this BD as long as the E bit is zero.
1 The buffer is not full. The CPM controls this BD and its buffer; do not modify this BD.
1
Ñ
Reserved, should be cleared.
2
W
Wrap (Þnal BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the Þrst BD that
RBASE points to. The number of BDs is determined only by the W bit and overall space constraints of
the dual-port RAM.
3
I
Interrupt. Note that this bit does not mask SCCE[RXF] interrupts.
0 No SCCE[RXB] interrupt is generated after this buffer is used.
1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the Ethernet controller. These two bits
can cause interrupts if they are enabled.
MOTOROLA
Table 28-6. PSMR Field Descriptions
2
3
4
5
W
I
L
F
Ñ
Rx Data Buffer Pointer
Figure 28-8. SCC Ethernet Receive RxBD
Chapter 28. SCC Ethernet Mode
Part V. The Communications Processor Module
Description
6
7
8
9
10
M
Ñ
LG
Data Length
Description
11
12
13
14
NO
SH
CR
OV
28-21
15
CL
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