Motorola MPC860 PowerQUICC User Manual page 424

Part IV. Hardware Interface
Bit 0 1
Field
HRESET
POR
R/W
Addr
Bit 16 17
Field SPLSS TEXPS Ñ TMIST
HRESET Ñ 1
POR 0 1
R/W
Addr
*
Depends on the combination of MODCK1and MODCK2. See Table 15-4 for more information.
Figure 15-16. PLL, Low-Power, and Reset Control Register (PLPRCR)
Table 15-9 described PLPRCR bits.
Bits Name
0Ð11 MF Multiplication factor. Determines the factor by which the OSCCLK input will be multiplied to produce
VCOOUT. This Þeld controls the value of the divider in the SPLL feedback loop. Programmable
between 1and 4096, where 0x000 corresponds to 1 and 0xFFF corresponds to 4096.
The MF Þeld can be read and written at any time. Changing the MF Þeld causes the SPLL to lose its
lock. All clocks are disabled until the SPLL reaches lock condition.
12Ð15 Ñ Reserved, should be cleared.
16 SPLSS System PLL Lock Status Sticky. Cleared by power-on reset. Not affected by hard reset. An
out-of-lock indication sets the SPLSS bit and it remains set until the software clears it. At power-on
reset, the state of the SPLSS bit is zero. Write a 1 to clear this bit (writing a zero has no effect). A
loss-of lock is caused by a change in the MF Þeld or the processor entering deep-sleep mode or
power-down mode. These three conditions do not affect the SPLSS bit.
0 =SPLL remains locked.
1 =SPLL has gone out of lock at least once since the bit was cleared.
17 TEXPS Timer Expired Status. Internal status bit set when the periodic timer expires, the real-time clock
alarm sets, the timebase clock alarm sets, the decrementer interrupt occurs, or the system resets.
This bit is cleared by writing a 1 (writing a zero has no effect). The TEXPS bit also controls the TEXP
signal. When TEXPS is set, the TEXP external signal is asserted and when it is reset, the TEXP
external signal is negated.
0 = TEXP is negated.
1 = TEXP is asserted.
18 Ñ Reserved, should be cleared.
15-30
2 3 4 5
MF
Ñ
*
(IMMR&0xFFFF0000) + 284
18 19 20 21
Ñ CSRC
0 0 0 0
0 0 0 0
(IMMR&0xFFFF0000) + 286
NOTE: HRESET is hard reset and POR is power-on reset.
Table 15-9. PLPRCR Field Descriptions
MPC860 PowerQUICC UserÕs Manual
6 7 8 9
R/W
22 23 24 25
LPM CSR LOLRE FIOPD
0 Ñ Ñ
0 0 0
R/W
Description
10 11 12 13 14
Ñ
0
0
26 27 28 29 30
Ñ
Ñ 0
0 0
MOTOROLA
15
31