Motorola MPC860 PowerQUICC User Manual page 961

Comparators perform compare on the instruction address (I-address), the load/store address
(L-address), and the load/store data (L-data) and can detect the following conditions:
¥ Equal to
¥ Not equal to
¥ Greater than
¥ Less than
Greater-than-or-equal-to and less-than-or-equal-to are easily obtained from these four
conditions. See Section 37.2.4.5, ÒGenerating Six Compare Types.Ó Using the AND-OR
logic structures Òin rangeÓ and Òout of rangeÓ detections (on address and data) are
supported. The counters can be used to program a breakpoint to be recognized after an event
is detected a predeÞned number of times.
The L-data comparators operate on load or store integer data. When operating on integer
data, L-data comparators perform comparisons on bytes, half-words, and words, treating
numbers as signed or unsigned. Comparators generate match events, then instruction match
events enter the instruction AND-OR logic where instruction watchpoints and breakpoints
are generated. An asserted instruction watchpoint can generate an instruction breakpoint.
Two different events can decrement one counter. When a counter on an instruction
watchpoint expires, the instruction breakpoint is asserted.
Instruction watchpoints and load/store match events on address/data enter the load/store
AND-OR logic where load/store watchpoints and breakpoints are generated. Load/store
watchpoints (when asserted) can generate the load/store breakpoint or decrement a counter.
When a counter on one load/store watchpoint expires, the load/store breakpoint is asserted.
Watchpoints progress in the machine and are reported on retirement. Internal breakpoints
progress in the machine until they reach the top of the history buffer, at which point the
machine branches to the breakpoint exception vector. To allow use of breakpoint features
without restricting software, the address of the load/store cycle that generated the load/store
breakpoint is not stored in the data address register (DAR). In a load/store breakpoint, the
address of the load/store cycle that generated the breakpoint is stored in the breakpoint
address register (BAR).
For more information, see Section 37.3, ÒDevelopment System Interface.Ó
37.2.3 Functional Description
The following sections describe instruction and load/store watchpoint generation in detail.
37.2.3.1 Instruction Support Detailed Description
Each of the four instruction address comparators (AÐD), shown in Figure 37-2, is 30 bits
long and generates two output signalsÑequal and less than. These signals generate one of
four eventsÑequal, not equal, greater than, or less than. The instruction watchpoints and
MOTOROLA Chapter 37. System Development and Debugging
Part VI. Debug and Test
37-11