Motorola MPC860 PowerQUICC User Manual page 790

Part V. The Communications Processor Module
1. ConÞgure the port A pins to enable TXD2 and RXD2. Set PAPAR[12, 13] and clear
PADIR[12, 13] and PAODR[12, 13].
2. ConÞgure the port C pins to enable RTS2, CTS2, and CD2. Set PCPAR[14] and
PCSO[8, 9] and clear PCPAR[8, 9] and PCDIR[8, 9, 14].
3. ConÞgure port A to enable CLK3. Set PAPAR[5] and clear PADIR[5].
4. Connect CLK3 to SCC2 using the serial interface. Set SICR[R2CS] and
SICR[T2CS] to 0b110.
5. Connect the SCC2 to the NMSI and clear SICR[SC2].
6. Initialize the SDMA conÞguration register (SDCR) to 0x0001.
7. Write RBASE with 0x0000 and TBASE with 0x0008 in the SCC2 parameter RAM
to point to one RxBD at the beginning of dual-port RAM followed by one TxBD.
8. Write 0x0041 to the CPCR to execute
9. Write RFCR and TFCR with 0x10 for normal operation.
10. Write MRBLR with the maximum number of bytes per receive buffer and assume
16-bytes, so MRBLR = 0x0010.
11. Write CRC_P with 0x0000_FFFF to comply with the 16-bit CRC-CCITT.
12. Write CRC_C with 0x0000_F0B8 to comply with the 16-bit CRC-CCITT.
13. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory.
Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length]
(optional), and 0x0000_1000 to RxBD[Buffer Pointer].
14. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and
contains Þve 8-bit characters. Write 0xBC00 to TxBD[Status and Control], 0x0005
to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].
15. Write 0xFFFF to SCCE to clear any previous events.
16. Write 0x0013 to SCCM to enable the TXE, TXB, and RXB interrupts.
17. Write 0x2000_0000 to CIMR so the SCC2 can generate a system interrupt. The
CICR should also be initialized.
18. Write 0x0000_1980 to GSMR_H2 to conÞgure the transparent channel.
19. Write 0x0000_0000 to GSMR_L2 to conÞgure CTS and CD to automatically
control transmission and reception (DIAG bits). Normal operation of the transmit
clock is used. Note that the transmitter (ENT) and receiver (ENR) are not enabled
yet.
20. Write 0x0000_0030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This
additional write ensures that the ENT and ENR bits are enabled last.
Note that after 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the
Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers)
condition since only one RxBD is prepared.
29-14
INIT RX AND TX PARAMETERS
MPC860 PowerQUICC UserÕs Manual
for SCC2.
MOTOROLA