Motorola MPC860 PowerQUICC User Manual page 432

Part IV. Hardware Interface
signals speciÞed in the RAM array is output on the corresponding UPM pins. See
Figure 16-4.
Address (A),
Address
Type (AT)
Address
Comparator
Bank Select
MS
Field
Figure 16-4. Basic Memory Controller Operation
16.3 Chip-Select Programming Common to the
GPCM and UPM
The GPCM and the UPMs use the memory controller registers as speciÞed in Table 16-1.
See Section 16.4, ÒRegister Descriptions,Ó for speciÞc register information.
Table 16-1. Memory Controller Register Usage
Base register bank 0Ð7 register (BRx)
Option register bank 0Ð7 register (ORx)
Memory status register (MSTAT)
Memory command register (MCR)
Machine A mode register (MAMR)
Machine B mode register (MBMR)
Memory data register (MDR)
Memory address register (MAR)
Memory periodic timer prescaler register (MPTPR)
16-6
Internal/External Memory Access Request Select
UPMA
Signals
Timing
Generator
Register
MPC860 PowerQUICC UserÕs Manual
UPMB GPCM
Signals
Timing
Generator
MUX
External Signals
Used by the GPCM
Ö
Ö
Ö
Used by a UPM
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
MOTOROLA