Table of Contents
Advertisement
data cache operation, 8-25
Ethernet mode, 28-3
external bus interface, 14-1
HDLC bus controller, 24-19
2
I
C controller, 32-2
IDMA emulation, 20-6
instruction cache operation, 8-22
memory controller, 16-1
MMU, 9-1
MPC860-specific features, 4-4
parallel I/O ports, 34-2
parallel interface port, 33-1
PowerPC architecture-defined, 4-2
SCC HDLC mode, 24-2
SCC UART mode, 23-2
serial communications controllers (SCCs), 22-2
serial interface, 21-3
serial management controllers (SMCs), 30-2
serial peripheral interface, 31-2
SIU, 11-1
SMC in transparent mode, 30-21
SMC in UART mode, 30-10
Transparent mode, 29-1
FIR library functions, DSP, 36-7
Freeze operation, 11-33
FRZ (freeze) signal, 3-6, 13-8
Full completion queue timing, 10-4
G
General-purpose chip-select machine (GPCM), 16-18
General-purpose signals, 16-40
GPL_Xn (general-purpose line) signal, 3-7, 13-10
GSMR (AppleTalk mode), 25-3
GSMR (general SCC mode register), 22-3
GSMR (general SCC mode register) (asynchronous
HDLC), 26-6
GSMR/DSR configuration for asynchronous HDLC
mode, 26-6
GSMR/PSMR
programming for HDLC bus protocol, 24-23
H
Hard reset configuration word, 12-9
HDLC bus controller, 24-16
HI-Z instruction, 38-7
HRESET
external, 12-2
hard reset configuration word, 12-9
internal, 12-2
reset configuration, 12-6, 12-6
reset sequence, 12-4
settings at power-on, 15-7
HRESET (hard reset) signal, 3-8, 13-11
MOTOROLA
INDEX
I
2
I2ADD (I
C address) register, 32-7
2
I2BRG (I
C baud rate generator) register, 32-7
2
I
C controller
buffer descriptors, 32-11
clocking, 32-2
commands, 32-11
master read (slave write), 32-4
master write (slave read), 32-3
overview, xxviii, 32-1
parameter RAM, 32-9
registers, 32-6
signals functions, 32-2
slave read (master write), 32-3
slave write (master read), 32-4
transfers, 32-3
2
I2CER (I
C event register), 32-8
2
I2CMR (I
C mask register), 32-8
2
I2COM (I
C command) register, 32-8
2
I2MOD (I
C mode) register, 32-6
IC_ADR (instruction cache address) register, 8-8
IC_CST (instruction cache control and status)
register, 8-6
IC_CST commands, 8-9
IC_DAT (instruction cache data port) register, 8-8
IDMA
serial performance considerations, B-4
TEA, 20-22
IDMA emulation, 20-5
IDMA host commands, 20-12
IDMA parameter RAM, 20-6
IDMA transfer, 20-21
IDMA transfers, 20-15
IDMR1 (IDMA1 mask register, single-buffer
mode), 20-20
IDMRs (IDMA mask registers), 20-9
IDSR1 (IDMA1 status register, single-buffer
mode), 20-19
IDSRs (IDMA status registers), 20-8
IEEE 1149.1 test access port
boundary scan register, 38-3
BSDL description, 38-8
overview, 38-1
recommended configuration, 38-8
TAP controller, 38-2
usage considerations, 38-7
IMMR (internal memory map register), 11-4
Instruction fetch show cycle, 37-3
Instruction support control (ICTRL) register, 37-39
Instruction timing, 10-1
list of instructions, 10-6
Instructions
branch and flow control
branch instruction address calculation, 6-15
Index
Index--5
Advertisement
Table of Contents
