Motorola MPC860 PowerQUICC User Manual page 445

Part IV. Hardware Interface
Option Register Attributes
TRLX Access ACS CSNT
0 Read 00
0 Read 10
0 Read 11
0 Write 00
0 Write 10
0 Write 11
0 Write 00
0 Write 10
0 Write 11
1 Read 00
1 Read 10
1 Read 11
1 Write 00
1 Write 10
1 Write 11
1 Write 00
1 Write 10
1 Write 11
1
SCY is the number of wait cycles from the option register.
16.5.1.1 Chip-Select Assertion Timing
The banks selected by the GPCM support an option to output CS at different timings with
respect to the external address bus. Depending on the value of the ACS Þeld (plus an
additional cycle if TRLX = 1), CS can be output as follows
¥ Simultaneous with the external address
¥ One quarter of a clock cycle later
¥ One half of a clock cycle later
Figure 16-16 shows a basic connection between the MPC860 and an external peripheral
device. Here, CS (the strobe output for the memory access) is connected directly to CE of
the memory device and R/W is connected to the respective R/W in the peripheral device.
16-19
Table 16-11. GPCM Strobe Signal Behavior
Address to CS
Asserted Address/Data Invalid
x 0
x 1/4*Clock
x 1/2*Clock
0 0
0 1/4*Clock
0 1/2*Clock
1 0
1 1/4*Clock
1 1/2*Clock
x 0
x (1+1/4)*Clock
x (1+1/2)*Clock
0 0
0 (1+1/4)*Clock
0 (1+1/2)*Clock
1 0
1 (1+1/4)*Clock
1 (1+1/2)*Clock
MPC860 PowerQUICC UserÕs Manual
Signal Behavior
CS Negated to WE Negated to
Address/Data Invalid
1/4* Clock
1/4*Clock
1/4*Clock
1/4*Clock
1/4*Clock
1/4*Clock
1/4*Clock
1/2*Clock
1/2*Clock
1/4*Clock
1/4*Clock
1/4*Clock
1/4*Clock
1/4*Clock
1/4*Clock
1/4*Clock 1+1/2*Clock
1+1/2*Clock 1+1/2*Clock
1+1/2*Clock 1+1/2*Clock
Total Cycles
x 2+SCY
x 2+SCY
x 2+SCY
1/4*Clock 2+SCY
1/4*Clock 2+SCY
1/4*Clock 2+SCY
1/2*Clock 2+SCY
1/2*Clock 2+SCY
1/2*Clock 2+SCY
x 2+2*SCY
x 3+2*SCY
x 3+2*SCY
1/4*Clock 2+2*SCY
1/4*Clock 3+2*SCY
1/4*Clock 3+2*SCY
3+2*SCY
4+2*SCY
4+2*SCY
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