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Part IV. Hardware Interface
17.3.1 Memory-Only Cards
Table 17-5 lists worst-case conditions of host programming memory cards and assumes
WAIT is not used. If it is, the minimum strobe time is at least 35 ns + 1 system clock.
Table 17-5. Host Programming for Memory Cards
Memory Access
1
Time
2
STP
Clock Cycle
100
20 ns (50 MHz)
6
30 ns (33.3 MHz)
4
40 ns (25 MHz)
3
62 ns (16 MHz)
2
83 ns (12 MHz)
2
1
Because the minimum hold time is one clock, the real access time is, access time + one clock.
2
Worst-case setup time (STP). The worst-case setup time is address to strobe.
3
Length (LNG) is the minimum strobe time.
4
Worst-case hold time (HLD). The worst-case hold time is data disable from OE.
17.3.2 I/O Cards
Table 17-6 lists worst-case conditions of host programming I/O cards.
Frequency
20 ns (50 MHz)
30 ns (33.3 MHz)
40 ns (25 MHz)
62 ns (16 MHz)
83 ns (12 MHz)
1
Setup time worst-case is for a write. In these cases, setup=data_set_up_before_iord +1 clock.
17.3.3 Interrupts
The PCMCIA interface input pins register (PIPR) reports any changes on inputs from the
PCMCIA card to the host (BVD, CD, RDY, VS). The contents of the PCMCIA interface
status changed register (PSCR) are logically ANDed with the PCMCIA interface enable
register (PER) to generate a PCMCIA interface interrupt. The interrupt level is user
programmable and the PCMCIA interface can generate an additional interrupt for
RDY/IRQ that can trigger on level (low or high) or edge (fall or rise) of the input signal.
17-6
600 ns
200 ns
3
4
LNG
HLD
STP
300
150
30
24
8
2
16
5
2
12
4
1
8
3
1
6
2
1
Table 17-6. Host Programming For I/O Cards
1
STP
60
4
3
3
2
2
MPC860 PowerQUICC UserÕs Manual
150 ns
LNG
HLD
STP
LNG
120
90
20
80
8
5
2
6
5
3
1
4
4
3
1
3
2
2
1
2
2
2
1
1
LNG
165
8
6
4
3
2
100 ns
HLD
STP
LNG
HLD
75
15
60
50
4
1
4
3
3
1
3
2
2
1
2
2
2
1
1
1
1
1
1
1
HLD
30
2
1
1
1
1
MOTOROLA
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