Motorola MPC860 PowerQUICC User Manual page 453

Clock
Address
TS
TA
CSx
CSy
R/W
OE
Data
Figure 16-28. GPCM Read Followed by Read from Same Bank (EHTR = 1)
16.5.2 Boot Chip-Select Operation
Boot chip-select operation allows address decoding for a boot ROM before system
initialization occurs. The CS0 signal is the boot chip-select output and its operation differs
from the other external chip-select outputs on system reset. When the MPC860 internal
core begins accessing memory at system reset, CS0 is asserted for every address, unless an
internal register is accessed.
The boot chip-select provides a programmable port size during system reset by using the
BPS Þeld of the hard reset conÞguration word described in. Setting these appropriately
allows a boot ROM to be located anywhere in the address space. The boot chip-select does
not provide write protection and responds to all address types. CS0 operates this way until
the Þrst write to OR0 and it can be used as any other chip-select register once the preferred
address range is loaded into BR0. After the Þrst write to OR0, the boot chip-select can only
be restarted on hardware reset. The initial values of the boot bank in the memory controller
are described in Table 16-12.
MOTOROLA
Hold Time
Chapter 16. Memory Controller
Part IV. Hardware Interface
16-27