Motorola MPC860 PowerQUICC User Manual page 804

Part V. The Communications Processor Module
30.3.10 SMC UART Receive BD (RxBD)
The CP reports information about the received data in each bufferÕs RxBD, shown in
Figure 30-6. The CP then closes the current buffer, generates a maskable interrupt, and
starts receiving data into the next buffer after one of the following occurs:
¥ An error is received during message processing
¥ A full receive buffer is detected
¥ A programmable number of consecutive idle characters are received
0 1
Offset + 0 E Ñ
Offset + 2
Offset + 4
Offset + 6
Table 30-8 describes SMC UART RxBD status and control Þelds.
Table 30-8. SMC UART RxBD Status and Control Field Descriptions
Bit Name
0 E Empty.
0 The buffer is full or data reception stopped due to an error. The core can read or write any Þelds of
this RxBD. The CP does not use this BD while E is zero.
1 The buffer is empty or reception is in progress. This RxBD and its buffer are owned by the CP. Once
E is set, the core should not write any Þelds of this RxBD.
1 Ñ Reserved, should be cleared
2 W Wrap (last BD in RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that
RBASE points to in the table. The number of RxBDs in this table is determined only by the W bit and
overall space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is Þlled.
1 The SMCE[RX] is set when this buffer is completely Þlled by the CP, indicating the need for the core
to process the buffer. RX can cause an interrupt if it is enabled.
4Ð5 Ñ Reserved, should be cleared
6 CM Continuous mode.
0 Normal operation.
1 The CP does not clear the E bit after this BD is closed, allowing the CP to automatically overwrite
the buffer when it next accesses the BD. However, E is cleared if an error occurs during reception,
regardless of how CM is set.
7 ID Buffer closed on reception of idles. Set when the buffer has closed because a programmable number
of consecutive idle sequences is received. The CP writes ID after received data is in the buffer.
8Ð9 Ñ Reserved, should be cleared
30-14
2 3 4 5
W I Ñ CM
Figure 30-6. SMC UART Receive BD (RxBD)
MPC860 PowerQUICC UserÕs Manual
6 7 8 9 10
ID Ñ BR
Data Length
Rx Buffer Pointer
Description
11 12 13 14
FR PR Ñ OV
MOTOROLA
15
Ñ